I'm not sure if I fully understood your intentions... There is a simple way to call individual SV functions from e, but you can also wrap complete UVCs so that the e env can instantiate and control a UVM-SV sequencer, driving sequences and transactions from e. There are examples for both, supplied in the tool installation as part of the SoC Verification Kit.
For the UVC wrapping, the example files live under <incisive-install-dir>/kits/VerificationKit/soc_verification_lib/mixed_ex_lib/e_over_sv_class_lib/
You can find a self-paced workshop with labs here: <incisive-install-dir>/doc/kit_topics/uvm_mixed/e_over_sv/workshop/Integrating_SV_UVC_in_e.pdf
If however you just want to do a simple function call interface, take a look at "Using e Method Ports with SystemVerilog Functions and Tasks" in the cdnshelp tool. It's under the hierarchy:
Specman Functional Verification -> Specman Integrators Guide -> Integrating the e testbench with SystemVerilog
Hope this helps.