Is there a way for the multiple-vdd and/or virtual vdd nets to be properly generated during verilogIn?
The import process relies on using the schematic and symbol definitions from the artisan_cell library that is provided to us and any cells that we have power gated or supplied a lower vdd to in the apr flow are not being properly reflected by the verilogIn process. (for example, you have an inv chain and say some of the inv are power gated (inv vdd is virtual) and the rest are not (inv vdd matches vdd supply), the schematic generated via verilogIn has all inverter's supply connected to vdd and the header is therefore unconnected). The layout/gds is correct, but lvs will be incorrect due to the schematic's difference.
Currently we're using a brute force method and creating new schematic/symbols with the accurate port information, which works for the small test designs we have made...but is very impractical for our whole project. Wondering if there is a better way to do this.
Any information/advice is appreciated!