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Power Difference between Analog Simulation and RTL complier estimation

Last post Tue, Apr 2 2013 9:31 AM by Fotios Nt. 1 replies.
 Started by GreenGraphene 25 Mar 2013 05:48 AM. Topic has 1 replies and 1435 views
• Mon, Mar 25 2013 5:48 AM

• GreenGraphene
• Joined on Tue, Apr 3 2012
• ERFURT, Thueringen
• Posts 6
• Points 75
Power Difference between Analog Simulation and RTL complier estimation
 Hallo, I am creating a standard cell library. I did analog simulation for cell design and estimated power values for the cells , lets say, NOT, NOR and NAND and I have their power values for static, dynamic, etc. Now based on that I created library file, and used that in RTL omplier for single cell designs and when i estimate the power it goes up to several orders and I am clueless of why this is so. Any suggestions or ideas ?? The operating conditions are verified for the same such as Freq, VDD, Load Cap., etc. Ex: for a 10nW in Virtuoso (Analog) estiamtion the equivalent estimation comes upto 80-90 nW in RTL power estimation.
• Post Points: 20
• Tue, Apr 2 2013 9:31 AM

• Fotios Nt
• Joined on Fri, Nov 18 2011
• Posts 5
• Points 55
Re: Power Difference between Analog Simulation and RTL complier estimation
 RTL compiler has a default value for input switching activitiy (i.e how fast inputs change)  Directly from the rc-lp manual:If you want a fast power analysis you can choose to apply the default switching activities.The tool default signal probability is 0.5, the tool default toggle rate is 0.02, and the defaulttoggle rate unit is per nanosecond.  If you simulate your cell using constants as an input, or a very low switching rate, you might get a huge difference. So, either change the input switching activity to what you have set in virtuoso, or do the oposite, and let us know  Fotis  edit: made response easier to read/understand
• Post Points: 5