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 ADEXL and VerilogA 

Last post Tue, Mar 19 2013 11:53 PM by Tobben24. 2 replies.
Started by Tobben24 19 Mar 2013 02:04 AM. Topic has 2 replies and 646 views
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  • Tue, Mar 19 2013 2:04 AM

    • Tobben24
    • Top 500 Contributor
    • Joined on Mon, Nov 26 2012
    • Posts 32
    • Points 535
    ADEXL and VerilogA Reply

    Hi,

    Is it possible to control variables defined in a veriloga symbol from adexl as a normal parameter? 

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    • Post Points: 20
  • Tue, Mar 19 2013 10:23 PM

    Re: ADEXL and VerilogA Reply

    If it's a parameter passed into the VerilogA model, I don't really understand what your issue is - that should just work?

    So maybe you'll need to elaborate?

    Regards,

    Andrew.

    • Post Points: 20
  • Tue, Mar 19 2013 11:53 PM

    • Tobben24
    • Top 500 Contributor
    • Joined on Mon, Nov 26 2012
    • Posts 32
    • Points 535
    Re: ADEXL and VerilogA Reply

    Hi,

     After some trying I found out that a parameter in VerilogA is overridable through the object property in schematic.

    • Post Points: 5
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Started by Tobben24 at 19 Mar 2013 02:04 AM. Topic has 2 replies.