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 Virtual Clock and Synthesize :) 

Last post Sat, Mar 16 2013 5:04 AM by Ram S. 0 replies.
Started by Ram S 16 Mar 2013 05:04 AM. Topic has 0 replies.
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  • Sat, Mar 16 2013 5:04 AM

    • Ram S
    • Not Ranked
    • Joined on Sat, Mar 16 2013
    • Posts 1
    • Points 5
    Virtual Clock and Synthesize :) Reply

    Hi everyone,

    I have couple of doubts. Please help me out. 

    1. My project is about SRAM design controller. While doing compilation i can able to see(in GUI) all my modules in my design but when i synthesize it one of the sub-module(Adress Decoder-FSM module) is not available. What will be the reason for it??

    2.How to define virtual clock for my combinational design module??

     Thanks in advance :) 
    • Post Points: 5
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Started by Ram S at 16 Mar 2013 05:04 AM. Topic has 0 replies.