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 synthesis warning of undriven signal 

Last post Mon, Mar 18 2013 7:34 AM by grasshopper. 1 replies.
Started by projectd2007 12 Mar 2013 01:45 AM. Topic has 1 replies and 848 views
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  • Tue, Mar 12 2013 1:45 AM

    synthesis warning of undriven signal Reply

     If there are some undriven signals in my design,can RTL-Compiler find that?

     Is there any synthesis "warning", "Info" or "Error about this issue?

    Should I set any attribure to find this problem?

     

     

    Here are some sample code:

    module mydesign (A, B) ;

    input [3:0] A;

    output [3:0] B;

    wire [1:0] undriven_signal;

    reg [5:0] reg_A;

     

    always@(*) begin

         case(A)

         4'd0: XXXXXX

         4'd1: XXXXXX

         4'd2: XXXXXX

         4'd3: XXXXXX

         4'd4: XXXXXX

         4'd5: XXXXXX

         4'd6: XXXXXX

         4'd7: XXXXXX

         4'd8: XXXXXX

         4'd9: XXXXXX

         4'd10: XXXXXX

         4'd11: XXXXXX

         4'd12: XXXXXX

         4'd13: XXXXXX

         4'd14: XXXXXX

         4'd15:  reg_A = {undriven_signal, A};

    end

    endmodule

     

    Warning : Undriven signal detected. [ELABUTL-125]

    This warning only tell me that reg_A has some undriven signals, but I want the tool tells me more about undriven_signal.

    The tool tells me that the warning location at line "case(A)". Can the tool find the line at "4'd15:  reg_A = {undriven_signal, A};"?

     

    • Post Points: 20
  • Mon, Mar 18 2013 7:34 AM

    • grasshopper
    • Top 25 Contributor
    • Joined on Fri, Jul 18 2008
    • Chelmsford, MA
    • Posts 242
    • Points 3,205
    Re: synthesis warning of undriven signal Reply

    As you pointed out, there are variaous ELABUTIL... messages to identify this situations. Some constructs provide more granularity than others but underiven signals are ALWAYS reported

     

    gh-

    • Post Points: 5
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Started by projectd2007 at 12 Mar 2013 01:45 AM. Topic has 1 replies.