I'd like to model a resistor in verilog ams using wreal. That is, I need the equivalent of the "tran" primitive that exists in vanilla verilog.
module res (p,n);
//need a model here, something like tran t1(p,n)
I've tried to check the inouts for the `wrealZState to determine what port is actually actually driving and set the signal direction accordingly but I couldn't get good simulation results.
Has anyone already solved this problem?