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 clock tree synthesis for clock gating 

Last post Tue, Mar 12 2013 1:34 AM by quiet. 6 replies.
Started by quiet 27 Feb 2013 01:49 AM. Topic has 6 replies and 1565 views
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  • Wed, Feb 27 2013 1:49 AM

    • quiet
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    clock tree synthesis for clock gating Reply

    I use clock gating in my design, but it seems the clock tree synthesis only balances the clock to the clock gating cell but not to the leaf register.

    I have checked the post-layout simulation results. The clock signals to the gating cell are well aligned. But the gated clock signals to the leaf register are not well aligned.

    Is there any solutions to let the tool balance the clock tree passing through the clock gating cell?

    Thanks.

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    • Post Points: 20
  • Wed, Feb 27 2013 6:30 AM

    • Yuqi
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    Re: clock tree synthesis for clock gating Reply

    Did you try the throughPin option in the clock specification file? Maybe it works.

    BR

    Yuqi 

    • Post Points: 20
  • Wed, Feb 27 2013 6:45 AM

    • quiet
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    Re: clock tree synthesis for clock gating Reply
    Because I use design compile to add the clock gating cells automatically, it's hard to specify all the throughPins.
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  • Wed, Feb 27 2013 6:49 AM

    • Kari
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    Re: clock tree synthesis for clock gating Reply
    CTS should trace through the clock gates. What does your clock spec file look like? Do you have "noGating no"?
    • Post Points: 20
  • Wed, Feb 27 2013 7:28 AM

    • quiet
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    Re: clock tree synthesis for clock gating Reply

    I just use the specification file that's generated by the tool automatically. Do i need to add more options?

    And the option nogating has been set to no.

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  • Fri, Mar 8 2013 12:46 PM

    • Kari
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    Re: clock tree synthesis for clock gating Reply
    Did buffering up to the leaf cells occur? If so, then the spec file is correct and working. Maybe it's just the skew results that you're not happy with? We'd need more information about the problem.
    • Post Points: 20
  • Tue, Mar 12 2013 1:34 AM

    • quiet
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    Re: clock tree synthesis for clock gating Reply

    I have a doubt about the clock gating.

    If the clock gating is used, the enable and data are actually bufferred by two different register. The enable is bufferred by the latch of the clock gating cell, and the data will be bufferred by the actual data register. But if the delay for the generated clock from gating cell to data register is large, the data maybe missed, since it should be sampled during the edge of clock, but now the clock is delayed for a certain time. Then how does it work? Is my understanding right?

    Thanks.

    • Post Points: 5
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Started by quiet at 27 Feb 2013 01:49 AM. Topic has 6 replies.