I have a doubt about the clock gating.
If the clock gating is used, the enable and data are actually bufferred by two different register. The enable is bufferred by the latch of the clock gating cell, and the data will be bufferred by the actual data register. But if the delay for the generated clock from gating cell to data register is large, the data maybe missed, since it should be sampled during the edge of clock, but now the clock is delayed for a certain time. Then how does it work? Is my understanding right?