I'm trying to verify the following property:
-- psl assert_p1: assert always ( (CS = st_idle) -> next eventually! ((CS = st_get_ack) or (CS = st_set_ack)) );
The section "Waveforms for Liveness Assertions" of chapter 9 on the document Formal Verifier User Guide says: "A failed liveness assertion has an associated counter-example in which there is an infinitely repeating sequence of non-satisfying states for the assertion." And this is exactly what the problem is. The property fails and the counter-example has a LoopMarker. I suppose I have to force IFV to verify for more time?
The DUT is a state machine implementation in which CS is a user-defined type signal representing the current state and st_idle, st_get_ack, st_set_ack, etc are states of the state machine. st_idle has a transition for itself until it matches a value for three different signals. The VHDL code of this behaviour is the following:
when st_idle =>
if ready_i = '1' and busy_s = '0' then
NS <= st_get_ack;
elsif ready_frame_i = '1' then
NS <= st_set_ack;
NS <= st_idle;The property above checks if
It's interesting that a property checking if states st_set_ack and st_get_ack are never achieved and failed as well:
-- psl assert_pn1: assert never ( (CS = st_get_ack) or (CS = st_set_ack) );
What can I do?