That's not going to be so easy then. I had thought you might be able to do:
lceExtract(cvId) ; to use the Virtuoso Layout Suite XL extractor
firstNet && forall(instTerm cdr(inst~>instTerms) instTerm~>net==firstNet)
But even that's not quite right. The problem is that lceExtract will probably not work in general if there's no schematic source, or on partly laid out designs.
Fundamentally you're going to have to extract the connections from the device and see whether the nets are all the same for all instTerms - something like that. If it had been done with layout XL, something like the above would be relatively straightforward (it would need some refinement to ensure that all the instTerms are actually present).