I have a symbol view which has bus notation for pins like A<1:10>, B<1:10> (imported from verilog).
But the corresponding schematic has single bit notation, like A<0>, A<1> etc...(imported from a spice netlist)
I want to modify the schematic, by creating the bus style notation and remove the single pins.
Is there an automatic way to accomplish this? If not, is there a predefined Cadence skill function which may help?