Home > Community > Forums > Custom IC Design > Exporting manufactured interconnect geometry including DFM effects


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Exporting manufactured interconnect geometry including DFM effects 

Last post Thu, Mar 7 2013 2:42 AM by Quek. 1 replies.
Started by ArnoSetagaya 26 Jan 2013 08:14 PM. Topic has 1 replies and 720 views
Page 1 of 1 (2 items)
Sort Posts:
  • Sat, Jan 26 2013 8:14 PM

    Exporting manufactured interconnect geometry including DFM effects Reply
    I have a GDS file (and the corresponding ICT technology file). I want to decode and process that GDS to export a list of all the actual metal/dielectric interconnect shapes that actually get manufactured. I don't mean the simple drawn boxes that are specified in the GDS layers, but the 3D shapes after the process effects are computed, which may thicken wires based on density and such.

    What workflow and tools can do that?

    I'm mostly looking for the interconnect wires, poly gates,  and vias, but exporting device details would also be great.

    I'm not even an EDA designer.. I'm actually a physicist and I'm hoping to use my own tools to analyze computer chip electrostatics using my own algorithms and code. To do that I need the 3D shapes that a design actually produces.

    I assume the start of any processing would be to load the GDS into Calibre, and the technology files can give me details about the layer thicknesses and positions for both metal and dielectrics. But the more I learn, the more I realize that these shapes aren't what get manufactured.. there's an entire (large!) set of DFM operations that MODIFY the GDS structures using complex rules to include the effects of CMP, width adjustments from litho, automatic (implicit) metal fills, and implicit added air gaps. I can see a lot of these rules in the ICT file documentation, but those aren't enough for me to actually compute all those (dozens!) of complex effects and adjustments myself.

    From reading, it seems like the fab DRC rulesets may include (custom) code to compute these perturbations (resizing wires, shifting boxes up and down for CMP, adding metal fills, etc). What tools do I need to take my GDS and ICT file and get these updated geometries? As a giant ASCII list of 3D metal boxes and dielectric boxes is fine.. I can deal with formats, but I don't know the WORKFLOW that can produce these shapes.

    Is there some core functionality in Calibre (or another Cadence tool) which loads the GDS and somehow queries the databases to spit out the modified chip geometry? (Maybe after giving them fab rulesets too?? I don't know.)

    Googling didn't help too much, but I got the hint about rulesets from some online discussion, so I am hoping someone can teach me some of these basics. I'm hoping the answer is something like "Calibre will do it all for you, just load in the data, run the fab ruleset, then use THIS export commands for the updated geometry."

    Thanks much for any help!
    • Post Points: 20
  • Thu, Mar 7 2013 2:42 AM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,083
    • Points 16,495
    Re: Exporting manufactured interconnect geometry including DFM effects Reply

    Hi ArnoSetagaya

    It seems that you would like to find a way to report the geometry (length, width, thickness) of layout shapes after accounting for manufacturing effects such as wire edge enlargement, erosion, etc. Perhaps our Litho Physical Analyzer and Litho Electrical Analyzer might be what you need.

    The usual parasitic extraction flow might not be what you need. It is basicially as follows:

    a. Using a gds file and LVS rule deck, use PVS to generate an input database for RLCK parasitic extractor QRC
    b. Use the input database in "a" and qrcTechFile to generate spice netlist containing parasitic RLCK

    qrcTechFile is generated using an ictfile which contains different sections to account for manuafacturing effects. During extraction, QRC reads in the info and modifies the width/thickness of layout shapes according to their proximity to neighbouring shapes. Finally parasitic resistance, capacitance and inductance (self and mutual) are calculated based on the modified shapes. As the final result is in the form of a netlist, it looks like it is not what you need.

    Best regards

    • Post Points: 5
Page 1 of 1 (2 items)
Sort Posts:
Started by ArnoSetagaya at 26 Jan 2013 08:14 PM. Topic has 1 replies.