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 Multiple SRAMs 1 data bus 

Last post Fri, Feb 1 2013 6:46 AM by padmaster. 1 replies.
Started by neseroth 25 Jan 2013 06:04 PM. Topic has 1 replies and 671 views
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  • Fri, Jan 25 2013 6:04 PM

    • neseroth
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    • Joined on Sat, Jan 26 2013
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    • Points 20
    Multiple SRAMs 1 data bus Reply

    I am creating a pcb with multiple srams connected to an FPGA on 1 data bus. I intend to clock the srams and the fpga at 150 MHz. I am concerned about what issues will arise when connecting mutliple srams to the same data bus (only 1 sram will have its output enabled at a time). For example should I worry about impedance matching each branch of the bus, will enabling and disabling the outputs of the SRAM's cause strange transients on the entire bus, will having the bus split cause loop currents to form, or anything else I can't think of?

     

    Thanks,

    James G 

    • Post Points: 20
  • Fri, Feb 1 2013 6:46 AM

    • padmaster
    • Top 150 Contributor
    • Joined on Mon, Mar 2 2009
    • Huntsville, AL
    • Posts 56
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    Re: Multiple SRAMs 1 data bus Reply

    May I suggest you post this question in the "Logic Design" forum? You might get better respone in that forum.

    • Post Points: 5
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Started by neseroth at 25 Jan 2013 06:04 PM. Topic has 1 replies.