I guess there is no automatic way. Cadence support suggested some parameters that killed some functionality and I was hoping for something that would not require changing the view one way that would not require manual effort. Experimenting we came out with a solution that I`ll share here.
* Tell the netlister to use the systemVerilog view for the digital controller top.
* Inside the ADE netlist options use the Stop View list and add systemVerilog to whatever else is needed for the analog schematics. Then the digital controller will show up as a black box. This eliminates all the internal pin checking. As I said the top level pins match the schematic, it is jsut the internal blocks theat don`t.
* Create a directory and inside it create a series of symbolic links. Each one should have as a name a SystemVerilog module. So controller_top.sv would point to .../library/controller_top/systemVerilog/verilog.sv, and controller_core.sv would point to ....../controler_core/systemVerilog/verilog.sv, and so on. (there are other ways to do this as well, via the -f option of irun, or via a file with several include statements)
* In the simulation options set the libext field to .v,.sv so that both SystemVerilog and Verilog are searched. In the -y field put in the symlinks directory. And also include with the -v or -y fields whatever models that the RTL views might need.
* Then tell the netlister to run and then start the VerilogAMS simulation.
Then you would need a netlister configuration for each type of simulation. One for UltraSim using schematics or perhaps VerilogAMS using schematic views. One for VerilogAMS with SystemVerilog, as described above.
I guess there is still a minor issue that any time I make a change to a systemVerilog view I get an error back when I save it. I probably would have trouble running a pure digital simulation from within virtuoso, but I usually do that from the command line anyways, so no harm there.