Home > Community > Forums > Logic Design > RTL Complier flow with clock gating and scan insertion

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 RTL Complier flow with clock gating and scan insertion 

Last post Fri, Jan 18 2013 9:23 AM by Terry2000. 2 replies.
Started by Terry2000 17 Jan 2013 07:20 AM. Topic has 2 replies and 1177 views
Page 1 of 1 (3 items)
Sort Posts:
  • Thu, Jan 17 2013 7:20 AM

    • Terry2000
    • Not Ranked
    • Joined on Tue, Dec 18 2012
    • Posts 11
    • Points 275
    RTL Complier flow with clock gating and scan insertion Reply

    Hello, 

    I've been struggling to scan insert and clock gate a small design, I believe I've been flowing the recommended flow:

    1. If I clock gate by setting "set_attribute lp_insert_clock_gating true" then "connect_chains" in the flow any flops that have been clock gated are not in the scan chain. They appear to fail the dft check because of the clock gaing cell.

    2. If I connect the chains first then clock gate using the command "clock_gating insert_in_netlist" this does all appear to work. However some of the scan flop are replaced with cells with an extra unnecessary enable added which is tied off with a 1'b1. 

    3. To remove the 1'b1 I have "set_attribute avoid false {TIE0XM TIE1XM}" and "insert_tiehilo_cells -hi TIE1XM -lo TIE0XM".
    Downstream I will be using EDI for the PnR, is it necessary to remove them here or will EDI cope (it appears to). I'm puzzled why the tool is adding this cell.

    Any idea's why this is happening?

    • Post Points: 20
  • Thu, Jan 17 2013 2:49 PM

    • bmiller
    • Top 200 Contributor
    • Joined on Tue, Oct 14 2008
    • Ottawa, Ontario
    • Posts 42
    • Points 570
    Re: RTL Complier flow with clock gating and scan insertion Reply

    Regarding (1)... have you defined an lp_clock_gating_test_signal attribute? This attribute tells the tool what to connect to the test pin of the CG cell.  Usually, you set this attribute to your shift_enable:

       define_dft shift_enable -active high -name SE ....

       set_attr lp_clock_gating_test_signal SE /des*/*

     If you didn't do this, then it is not surprising that DFT rule checks fail after clock gating is inserted, because a clock gater without a test "override" creates an uncontrollable clock.

    Be sure you are running check_dft_rules BEFORE synthesis, and be sure it is clean.  You can check DFT rules again after synthesis, but if you don't run it before, your flops will NOT be mapped to scan flops.

     Regarding (2), I don't often use clock_gating insert_in_netlist.  This tends to result in poor clock gating coverage, and is only recommended if you don't have the option of starting from RTL.

     

    • Post Points: 20
  • Fri, Jan 18 2013 9:23 AM

    • Terry2000
    • Not Ranked
    • Joined on Tue, Dec 18 2012
    • Posts 11
    • Points 275
    Re: RTL Complier flow with clock gating and scan insertion Reply

     Hello,

    Thanks for you reply, I did have that attribute set but I'd messed up on the syntax !

    I got it working last night with by using the test mode signal:

             set_attribute lp_clock_gating_test_signal scan_mode_in /designs/$ec::MODULE

    Then I tried your method today and this worked also:

             set_attribute lp_clock_gating_test_signal SE /designs/$ec::MODULE

    Thanks again for your help.

     

     

    • Post Points: 5
Page 1 of 1 (3 items)
Sort Posts:
Started by Terry2000 at 17 Jan 2013 07:20 AM. Topic has 2 replies.