In our previous designs I would append a \\ to the end of a net alias to signify that it is active low. Example; OUTPUT ENABLE\\
Now I find that the "\\" is considered an illegal character so I have two questions
1. I'm open for suggestions as to a different approach on how to show that the net is active low within the net alias
2. Is there a way to catch these "illegal net names" in Capture before I go and import the logic into PCB Editor. I have run all sorts of error checking in capture and these nets do not come up as being problems.