This is my first post. So, I hope I'm writting it in the correct place.
I need a help to verify two concurrent modules (A and B) instantiated in a top module (Top). The concurrent modules implements a state machine and I want to verify if a given signal is 1, the module A is on state x and B is on state y. Is this possible?
Currently I can verify isolated modules using vunit. I defined the default clock and I wrote a set of properties for each module. But I can't write properties of two design units. I tried to use the inherit option with the verif_unit_name defined on the vunit of the modules A and B, but unsuccessfully.
Thanks in advance,