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 Verification of concurrent modules with IFV 

Last post Wed, Jan 9 2013 4:05 PM by Wesh. 0 replies.
Started by Wesh 09 Jan 2013 04:05 PM. Topic has 0 replies and 691 views
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  • Wed, Jan 9 2013 4:05 PM

    • Wesh
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    • Joined on Wed, Jan 9 2013
    • Posts 2
    • Points 40
    Verification of concurrent modules with IFV Reply
    Hi guys,
     
    This is my first post. So, I hope I'm writting it in the correct place. 
     
    I need a help to verify two concurrent modules (A and B) instantiated in a top module (Top). The concurrent modules implements a state machine and I want to verify if a given signal is 1,  the module A is on state x and B is on state y. Is this possible?

    Currently I can verify isolated modules using vunit. I defined the default clock and I wrote a set of properties for each module. But I can't write properties of two design units.  I tried to use the inherit option with the verif_unit_name defined on the vunit of the modules A and B, but unsuccessfully.

    Thanks in advance,

    My regards,
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Started by Wesh at 09 Jan 2013 04:05 PM. Topic has 0 replies.