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 soi transistor 

Last post Mon, Jan 7 2013 1:53 AM by Andrew Beckett. 3 replies.
Started by arundevnkumar 06 Jan 2013 12:02 AM. Topic has 3 replies and 776 views
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  • Sun, Jan 6 2013 12:02 AM

    soi transistor Reply

    i want to draw layout(Full custom) for SOI transistor using 180nm technology.Is it possible?

    • Post Points: 20
  • Sun, Jan 6 2013 12:49 AM

    Re: soi transistor Reply
    What a strange question! Why would you think this is not possible?
    • Post Points: 5
  • Sun, Jan 6 2013 9:10 PM

    Re: soi transistor Reply
    in ordinary cmos well is required to draw the layout.For soi transistor well is not required .Then from where i have to start.if you have any procedure,please send me.
    • Post Points: 20
  • Mon, Jan 7 2013 1:53 AM

    Re: soi transistor Reply

    Typically the documentation (e.g. DRM) for any technology would tell you what layers need to be drawn to make each device, plus the design rules for those layers.

    Also, most technologies would have a process design kit (PDK) which contained pcells (or sample layouts) for each type of device.

    Regards,

    Andrew.

    • Post Points: 5
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Started by arundevnkumar at 06 Jan 2013 12:02 AM. Topic has 3 replies.