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 EDI -> Empty Modules 

Last post Wed, Jan 29 2014 3:54 PM by Kabal. 7 replies.
Started by Terry2000 04 Jan 2013 07:59 AM. Topic has 7 replies and 4606 views
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  • Fri, Jan 4 2013 7:59 AM

    • Terry2000
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    • Joined on Tue, Dec 18 2012
    • Posts 11
    • Points 275
    EDI -> Empty Modules Reply

    Hello, 

    First run through EDI 12.00 and I'm having a few teething problems.

    Successfully synthesised the RTL to verilog netlist but when I import the design I'm getting the following warnings (all standard cells are in the verilog netlist are listed, I've trucated the listing for the post).

    I've checked the LEF and the cells are included.

     Any ideas what I'm doing wrong?

    **WARN: (ENCDB-2504):    Cell OR6M2XM is instantiated in the Verilog netlist, but is not defined.
    **WARN: (ENCDB-2504):   Cell OR4M1XM is instantiated in the Verilog netlist, but is not defined.
    **WARN: (ENCDB-2504):   Cell NR3M1XM is instantiated in the Verilog netlist, but is not defined.
    **WARN: (ENCDB-2504):   Cell AO31M2XM is instantiated in the Verilog netlist, but is not defined.
    **WARN: (ENCDB-2504):   Cell DFQRM1XM is instantiated in the Verilog netlist, but is not defined.
    WARN: (EMS-63):       Message <ENCDB-2504> has exceeded the default message display limit of 20.

    Found empty module (OR6M2XM).
    Found empty module (OR4M1XM).
    Found empty module (NR3M1XM).
    Found empty module (AO31M2XM).
    Found empty module (DFQRM1XM).
    Starting recursive module instantiation check.
    No recursion found.
    Term dir updated for 0 vinsts of 85 cells.
    Building hierarchical netlist for Cell hlt5000_toplevel ...
    *** Netlist is unique.
    ** info: there are 91 modules.
    ** info: there are 0 stdCell insts.
     

    • Post Points: 35
  • Fri, Jan 4 2013 9:09 AM

    • wally1
    • Top 50 Contributor
    • Joined on Mon, Aug 4 2008
    • Bellevue, WA
    • Posts 151
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    Re: EDI -> Empty Modules Reply

    Can you review the log and confirm the LEF was read in successfully? Make sure you list the technology LEF first followed by any additional LEF files.

    Thanks,

    Brian

    • Post Points: 20
  • Fri, Jan 4 2013 11:31 AM

    • Terry2000
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    • Joined on Tue, Dec 18 2012
    • Posts 11
    • Points 275
    Re: EDI -> Empty Modules Reply

    Hello,

    Thanks for your reply, good point because I can't see the lef being read in the log. The lef file however is being correctly add to the form.

    I've added a snippet of the log file and a snippet of the lef file.  I'm no expert on lef files, does it look correct?

    Log file ->

    Reading netlist ...
    Backslashed names will retain backslash and a trailing blank character.
    Reading verilog netlist 'r2g_output/r2g.v'
    Inserting temporary buffers to remove assignment statements.

    *** Memory Usage v#16 (Current mem = 368.211M, initial mem = 73.984M) ***
    *** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=368.2M) ***
    Set top cell to hlt5000_toplevel.
    *** End library_loading (cpu=0.00min, mem=0.0M, fe_cpu=0.09min, fe_real=1.43min, fe_mem=368.2M) ***

    {DETAILMESSAGE}**WARN: (ENCDB-2504):    Cell OR6M2XM is instantiated in the Verilog netlist, but is not defined.

    LEF file ->

    MACRO OR6M2XM
        CLASS CORE ;
        FOREIGN OR6M2XM 0 0 ;
        ORIGIN 0.0000 0.0000 ;
        SIZE 2.6000 BY 1.4000 ;
        SYMMETRY X Y ;
        SITE CORE ;
        PIN B
            DIRECTION INPUT ;
            ANTENNAMODEL OXIDE1 ;
            ANTENNAGATEAREA 0.0252  LAYER ME1  ;
            PORT
            LAYER ME1 ;
            RECT  2.0500 0.5850 2.1550 1.0400 ;
            END
        END B
        PIN A
            DIRECTION INPUT ;
            ANTENNAMODEL OXIDE1 ;
            ANTENNAGATEAREA 0.0252  LAYER ME1  ;
            PORT
            LAYER ME1 ;
            RECT  2.4400 0.4550 2.5500 0.8700 ;
            END
        END A
        PIN C
            DIRECTION INPUT ;
            ANTENNAMODEL OXIDE1 ;
            ANTENNAGATEAREA 0.0252  LAYER ME1  ;
            PORT
            LAYER ME1 ;
            RECT  1.8000 0.6500 1.9600 0.9900 ;
            END
        END C
        PIN D
            DIRECTION INPUT ;
            ANTENNAMODEL OXIDE1 ;
            ANTENNAGATEAREA 0.0252  LAYER ME1  ;
            PORT
            LAYER ME1 ;
            RECT  0.6500 0.6100 0.9600 0.7900 ;
            END
        END D
        PIN E
            DIRECTION INPUT ;
            ANTENNAMODEL OXIDE1 ;
            ANTENNAGATEAREA 0.0252  LAYER ME1  ;
            PORT
            LAYER ME1 ;
            RECT  0.3900 0.6200 0.5500 1.0000 ;
            END
        END E
        PIN F
            DIRECTION INPUT ;
            ANTENNAMODEL OXIDE1 ;
            ANTENNAGATEAREA 0.0252  LAYER ME1  ;
            PORT
            LAYER ME1 ;
            RECT  0.0500 0.6100 0.2600 0.8500 ;
            END
        END F
        PIN Z
            DIRECTION OUTPUT ;
            ANTENNADIFFAREA 0.1436  LAYER ME1  ;
            PORT
            LAYER ME1 ;
            RECT  1.2500 0.2600 1.5250 0.3900 ;
            RECT  1.2500 0.2600 1.3550 1.1900 ;
            END
        END Z
        PIN VDD
            DIRECTION INOUT ;
            USE POWER ;
            SHAPE ABUTMENT ;
            PORT
            LAYER ME1 ;
            RECT  0.0000 1.2950 2.6000 1.5050 ;
            RECT  1.5800 0.8800 1.7100 1.5050 ;
            RECT  0.9650 1.0600 1.0950 1.5050 ;
            RECT  0.0550 1.0300 0.1850 1.5050 ;
            END
        END VDD
        PIN VSS
            DIRECTION INOUT ;
            USE GROUND ;
            SHAPE ABUTMENT ;
            PORT
            LAYER ME1 ;
            RECT  0.0000 -0.1050 2.6000 0.1050 ;
            RECT  2.4350 -0.1050 2.5450 0.3450 ;
            RECT  1.8750 -0.1050 2.0450 0.3050 ;
            RECT  0.8950 -0.1050 1.0250 0.3250 ;
            RECT  0.3150 -0.1050 0.4450 0.3250 ;
            END
        END VSS
        OBS
            LAYER ME1 ;
            RECT  0.0550 0.1950 0.1850 0.5200 ;
            RECT  0.5750 0.1950 0.7300 0.5200 ;
            RECT  0.0550 0.4300 1.1500 0.5200 ;
            RECT  1.0600 0.4300 1.1500 0.9700 ;
            RECT  0.7550 0.8800 1.1500 0.9700 ;
            RECT  0.7550 0.8800 0.8650 1.1700 ;
            RECT  1.6200 0.1950 1.7650 0.4950 ;
            RECT  2.1350 0.1950 2.3450 0.4950 ;
            RECT  1.6200 0.3950 2.3450 0.4950 ;
            RECT  1.6200 0.1950 1.7100 0.7000 ;
            RECT  1.4650 0.5700 1.7100 0.7000 ;
            RECT  2.2450 0.1950 2.3450 1.1500 ;
            RECT  2.2450 1.0200 2.5450 1.1500 ;
            LAYER SPSHVT ;
            RECT  0.0000 0.0000 2.6000 1.4000 ;
        END
    END OR6M2XM

     

    • Post Points: 20
  • Fri, Jan 4 2013 12:40 PM

    • wally1
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    • Bellevue, WA
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    Re: EDI -> Empty Modules Reply

    In the log file look for something like the following to indicate the LEF is being read in:

    Normal 0 false false false EN-US X-NONE X-NONE

    /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Calibri","sans-serif"; mso-fareast-font-family:Calibri; mso-bidi-font-family:"Times New Roman";}

         Loading LEF file LIBS/lef/gsclib045.fixed.lef...

    If you don't see that make sure you defined the following before init_design:

    Normal 0 false false false EN-US X-NONE X-NONE

     

    /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Calibri","sans-serif"; mso-fareast-font-family:Calibri; mso-bidi-font-family:"Times New Roman";}      set init_lef_file  list_of_lef_files

    Hope this helps,

    - Brian

     

    • Post Points: 5
  • Fri, Jan 4 2013 1:56 PM

    • Terry2000
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    • Joined on Tue, Dec 18 2012
    • Posts 11
    • Points 275
    Re: EDI -> Empty Modules Reply

    Hello,

    I've had a look at the cmd file generated using the file->import design. If I've understood correctly for some reason the init_lef_file variable is being set correctly then cleared.

    *** Memory pool thread-safe mode activated.
    <CMD> set conf_ioOri R0
    <CMD> set defHierChar /
    <CMD> set delaycal_input_transition_delay 0.1ps
    Set Input Pin Transition Delay as 0.1 ps.
    <CMD> set init_assign_buffer 1
    <CMD> set init_import_mode { -keepEmptyModule 1 -timerMode 1 -treatUndefinedCellAsBbox 0}
    <CMD> set init_lef_file /libs/UMC/UMxxxLSCSPMVBDS_A01/lef/uxxxlscspmvbds.lef
    <CMD> set init_oa_search_lib {}
    <CMD> set init_top_cell toplevel
    <CMD> set init_verilog r2g_output/r2g.v
    <CMD> set lsgOCPGainMult 1.000000
    <CMD> set rtl_vhdl_list {{WORK {WORK ../RTL/adc_interface.vhd ../RTL/fuse_control.vhd ../RTL/fuse_interface.vhd ../RTL/i2c_interface.vhd ../RTL/package.vhd}} {TEMP {}}}
    <CMD> set init_lef_file {}
    <CMD> init_design
    Reading netlist ...

     I entered the commands on the command line without the set init_lef_file {} and it's now trying to load the lef, it's moaning about it but at least  it's attempting to load. Thanks again for your help. 

    Loading LEF file /libs/UMC/UMxxxLSCSPMVBDS_A01/lef/uxxxlscspmvbds.lef...
    **ERROR: (ENCLF-328):   The layer 'ME1' specified in macro pin 'XOR4M8XM.A' does                                                                                    not exist
    **ERROR: (ENCLF-53):    The layer 'ME1' referenced in pin 'A' in macro 'XOR4M8XM                                                                                   ' is not found in the database. A layer must be defined in the LEF technology LA                                                                                   YER section before it can be referenced.

    • Post Points: 20
  • Fri, Jan 4 2013 2:15 PM

    • wally1
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    • Bellevue, WA
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    Re: EDI -> Empty Modules Reply

    If you are reading in a gate level netlist then use File->Import Design form, not the Import RTL form. Give this a try from the command line:

    set conf_ioOri R0
    set defHierChar /
    set delaycal_input_transition_delay 0.1ps
    set init_assign_buffer 1
    set init_import_mode { -keepEmptyModule 1 -timerMode 1 -treatUndefinedCellAsBbox 0}
    set init_lef_file /libs/UMC/UMxxxLSCSPMVBDS_A01/lef/uxxxlscspmvbds.lef
    set init_oa_search_lib {}
    set init_top_cell toplevel
    set init_verilog r2g_output/r2g.v
    set lsgOCPGainMult 1.000000
    init_design

    • Post Points: 5
  • Mon, Jan 7 2013 11:16 PM

    • nannasin28
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    • Posts 10
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    Re: EDI -> Empty Modules Reply
    I've added a snippet of the log file and a snippet of the lef file.
    MAX232
    http://www.hqew.net
    • Post Points: 20
  • Wed, Jan 29 2014 3:54 PM

    • Kabal
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    Re: EDI -> Empty Modules Reply

    nannasin28 

    Your company is using very "interesting" product marketing style... 

    • Post Points: 5
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Started by Terry2000 at 04 Jan 2013 07:59 AM. Topic has 7 replies.