Well, i just did some trials, that is what i did:
- I created a new cell view with verilogA type (since the availlable models are verilogA in the Berkeley site)
- This will generate for you the basic terminals of the device s,d,g,e , then u can creat a and save it.
- Then open a schematic cell view, and insert yr new FinFET symbol (u just created) in whatever topology.
- There is a parameter files for n-type and p-type u have to attache them otherwise when u run the simulation they would appear as undefined design varialbles that u have to put them manually.
- I performed a DC and Transient simulation however i had some problems doing AC analysis.
I am not sure about what i did right or not or missed something....!!
I dont think that my cadence version support BSIMCMG as abuilt in library
Also i think that Synopsys , HSPICE supports CMG libraries too.