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 Convert schematic to Verilog file 

Last post Wed, Jan 9 2013 3:33 AM by Myskill. 10 replies.
Started by Myskill 30 Dec 2012 10:33 PM. Topic has 10 replies and 2831 views
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  • Sun, Dec 30 2012 10:33 PM

    • Myskill
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    • Joined on Thu, Nov 8 2012
    • hyderabad, Andhra Pradesh
    • Posts 12
    • Points 310
    Convert schematic to Verilog file Reply

     Hi All,

                could you please help how to get verilog file from schematic.

     

    Regards,

    Rambabu

    • Post Points: 35
  • Mon, Dec 31 2012 4:18 AM

    Re: Convert schematic to Verilog file Reply

    Either Tools->NC Verilog (from the CIW), or  Launch->Simulation->NC Verilog (from a schematic).

    Andrew.

    • Post Points: 20
  • Fri, Jan 4 2013 2:37 AM

    • Myskill
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    • Joined on Thu, Nov 8 2012
    • hyderabad, Andhra Pradesh
    • Posts 12
    • Points 310
    Re: Convert schematic to Verilog file Reply

    Any shell command for generating verilog code from schematic hierarchically from top cell to bottom

     

    • Post Points: 20
  • Fri, Jan 4 2013 2:51 AM

    Re: Convert schematic to Verilog file Reply

     Set it up in the UI as described above, and then you can do:

    si -command netlist -batch pathToRunDirectory

    Andrew.

    • Post Points: 20
  • Sun, Jan 6 2013 9:27 PM

    • Myskill
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    • hyderabad, Andhra Pradesh
    • Posts 12
    • Points 310
    Re: Convert schematic to Verilog file Reply

     I am following following procedure for creation oa2verilog  

    Open a shell from the library manager using File->Open shell window. This shell will be initialized with the necessary environment variables for the next step.

    In the new shell use:

    oa2verilog -lib <name of library> -cell <name of cell> -view schematic -verilog <name of cell>.v -recursive

    Substitute the lib name and cell name for the specific cell to netlist.

    This is limited to a cell without hierarchy

     I want generate it for hierachy Could you please help on this.

    Regards,

    Rambabu

    • Post Points: 20
  • Mon, Jan 7 2013 1:47 AM

    Re: Convert schematic to Verilog file Reply

    I already explained how to do this with the Verilog netlister. oa2verilog is much lower level and does not support all of the complex control that the OSS Verilog netlister does. I would not recommend  you trying to use oa2verilog (it doesn't have the concept of switch and stop list, for example, nor does it support config views).

    Andrew.

    • Post Points: 5
  • Mon, Jan 7 2013 1:48 AM

    Re: Convert schematic to Verilog file Reply

    And you can tell this by the very small amount of coverage of oa2verilog in the documentation (search in cdnshelp and you'll see what I mean).

    Andrew.

    • Post Points: 20
  • Mon, Jan 7 2013 11:18 PM

    • nannasin28
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    • <?xml version="1.0" encoding="utf-16"?><string>shenzhen, Guangdong</string>
    • Posts 10
    • Points 80
    Re: Convert schematic to Verilog file Reply
    This shell will be initialized with the necessary environment variables for the next step.
    BS170
    http://www.hqew.net
    • Post Points: 5
  • Tue, Jan 8 2013 4:17 AM

    • Myskill
    • Not Ranked
    • Joined on Thu, Nov 8 2012
    • hyderabad, Andhra Pradesh
    • Posts 12
    • Points 310
    Re: Convert schematic to Verilog file Reply

    Hi all,
    This might be the most comon problem/task for ASIC engineers. I need a script that will generate a top level module for 'n' verilog modules (in 'n' files)

    Say I have A.v & B.v. The script should generate a ABTop.v such that

    module ABTop(
    clk
    :
    :
    );

    input clk;
    input (etc etc)
    :
    :
    output (etc etc)
    :
    :

    A A_i (
    .clk (clk)
    :
    :
    :
    );

    B B_i (
    .clk (clk)
    :
    :
    :
    );

    endmodule

    if there is any shell command for automation, please suggest me.

    Regards,

    Rambabu

     

    • Post Points: 20
  • Tue, Jan 8 2013 4:34 AM

    Re: Convert schematic to Verilog file Reply

    The Verilog netlister (using "si") can do this. This is covered in solution 1839821 . The quick executive summary is that you can put:

    vlogifCompatibilityMode = "4.0"

    in your .simrc (or .cdsinit if using Virtuoso). It will then create a single Verilog netlist (concatenated from the individual pieces that the verilog netlister normally produces).

    Regards,

    Andrew.

    • Post Points: 20
  • Wed, Jan 9 2013 3:33 AM

    • Myskill
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    • Joined on Thu, Nov 8 2012
    • hyderabad, Andhra Pradesh
    • Posts 12
    • Points 310
    Re: Convert schematic to Verilog file Reply

     Thank you Aandrew for your help

    Regards,

    Rambabu

    • Post Points: 5
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Started by Myskill at 30 Dec 2012 10:33 PM. Topic has 10 replies.