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 Transistors in series 

Last post Mon, Jan 27 2014 5:10 AM by Andrew Beckett. 7 replies.
Started by Glir 14 Dec 2012 08:24 AM. Topic has 7 replies and 4046 views
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  • Fri, Dec 7 2012 8:57 AM

    • Glir
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    Transistors in series Reply

    Hi! First of all, sorry if I'm posting it in the wrong place. Moderator please move it to the right place.

     

    My question is: when I change the multiplicity or the number of finger in a FET transistor, it means I'm putting them in parallel.

    My question is how I put them in series, without doing it manually.

    Thanks. 

    • Post Points: 5
  • Fri, Dec 14 2012 8:24 AM

    • Glir
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    Transistors in series Reply

    Hi! First of all, sorry if I'm posting it in the wrong place. Moderator please move it to the right place.

     

    My question is: when I change the multiplicity or the number of finger in a FET transistor, it means I'm putting them in parallel.

    My question is how I put them in series, without doing it manually.

    Thanks. 

    • Post Points: 5
  • Fri, Dec 14 2012 8:25 AM

    • Glir
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    Transistors in Series in Cadence Reply

    Hi! How are you?

     

    My question is: when I change the multiplicity or the number of finger in a FET transistor, it means I'm putting them in parallel.

    My question is how I put them in series, without doing it manually.

     

    Please explain carefully 'cause i'm pretty new to Cadence. 

    Thanks. 

    • Post Points: 20
  • Sat, Dec 15 2012 7:57 AM

    Re: Transistors in Series in Cadence Reply

    The Forum Guidelines tell you not to post the same question in more than one thread, so I've merged these two together.

    It's possible that some PDKs provide a mechanism for specifing series connected transistors (this is likely if using a finfet model such as bsimcmg). However, in general you'd probably have to do this by using iterated instances.

    Say that you wanted to have the devices in series with 10 in series, you'd call the instance M1<9:0> and then have the drain labelled something like drain,mid<8:0> and the source labelled mid<8:0>,source. What this would mean is that M1<9> would have it's drain connected to drain and source connected to mid<8>, then M1<8> would have it's drain connected to mid<8> and source to mid<7> and so on until M1<0> which would have it's drain connected to mid<0> and source connected to source.

    I've included a picture (I used the h bindkey to show where labels were attached).

    Regards,

    Andrew.


    • Post Points: 35
  • Fri, Jan 24 2014 9:23 AM

    • The Setlaz
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    Re: Transistors in Series in Cadence Reply

    Hi Andrew,

     

    I tried this trick and while it works just fine with a resistor, it does not do it for a transistor.

    Basically, it does not netlist correctly.

     

    I put 20 devices in series to create a cellview with pins D G S B, and when netlisting like you do, I have

    M1<19> ( D G S B )  params...

    M1<18> ( S G VDNext<18> B )  params...

    M1<17> ( VDNext<18> G VDNext<17> B )  params... 

    ...

    M1<1> ( VDNext<1> G VDNext<0> B )  params...   

    M1<0> ( VDNext<0> G S B )  params...   

     

    See how device <19> gets connected directly to the pins instead of going to the next device ? Hence I end up with 1 transistor and 19 dummies in series...

     

    To overcome this, I have to add a bus connecting the Source to the Drain, named VDNext<18:0> to get it as expected

    M1<19> ( D G VDNext<18> B )  params...

    M1<18> ( VDNext<18> G VDNext<17> B )  params...

    M1<17> ( VDNext<17> G VDNext<16> B )  params... 

    ...

    M1<1> ( VDNext<1> G VDNext<0> B )  params...

    M1<0> ( VDNext<0> G S B )  params...   

     

    Is this something wrong in my PDK or a bug or something ?
    I have no idea why if I remove the wire that connects source to drain, it does not netlist properly... For me, it's should be exactly the same to put it or not.

     

    Thanks,
    Damien

    • Post Points: 20
  • Sat, Jan 25 2014 5:55 PM

    Re: Transistors in Series in Cadence Reply

     Hi Damien,

    Are you sure you labelled the nets correctly? I don't see a need to put a wire between the two. I just drew the attached picture, and got this (spectre netlist):

    // Library name: opamp090
    // Cell name: itertran
    // View name: schematic
    M1\<19\> (D G VDNext\<18\> B) gpdk090_nmos1v w=(120n) l=100n as=69.6f \
            ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<18\> (VDNext\<18\> G VDNext\<17\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<17\> (VDNext\<17\> G VDNext\<16\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<16\> (VDNext\<16\> G VDNext\<15\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<15\> (VDNext\<15\> G VDNext\<14\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<14\> (VDNext\<14\> G VDNext\<13\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<13\> (VDNext\<13\> G VDNext\<12\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<12\> (VDNext\<12\> G VDNext\<11\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<11\> (VDNext\<11\> G VDNext\<10\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<10\> (VDNext\<10\> G VDNext\<9\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<9\> (VDNext\<9\> G VDNext\<8\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<8\> (VDNext\<8\> G VDNext\<7\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<7\> (VDNext\<7\> G VDNext\<6\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<6\> (VDNext\<6\> G VDNext\<5\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<5\> (VDNext\<5\> G VDNext\<4\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<4\> (VDNext\<4\> G VDNext\<3\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<3\> (VDNext\<3\> G VDNext\<2\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<2\> (VDNext\<2\> G VDNext\<1\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<1\> (VDNext\<1\> G VDNext\<0\> B) gpdk090_nmos1v w=(120n) l=100n \
            as=69.6f ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)
    M1\<0\> (VDNext\<0\> G S B) gpdk090_nmos1v w=(120n) l=100n as=69.6f \
            ad=69.6f ps=1.04u pd=1.04u m=(1)*(1)

     As you can see, that's correct and not how you describe. I can't see how a PDK could cause this to mess up - it would be pretty hard to make it misbehave!

    Regards,

    Andrew.


    • Post Points: 20
  • Mon, Jan 27 2014 1:07 AM

    • The Setlaz
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    Re: Transistors in Series in Cadence Reply

     Hi Andrew,

     

    I tried again replicating exactly your schematic and it worked.

     

    The only thing I had differently was my pins were places vertically and I separated the D pin from the 20 devices with a 'thru' connec.

    So the pin were not exactly labelled as you did, I guess that was the source of error.

     Thanks for putting it straight :)

     

    Damien

    • Post Points: 20
  • Mon, Jan 27 2014 5:10 AM

    Re: Transistors in Series in Cadence Reply

    Damien,

    You have to have a bend in the wire whenever you change the net name to tap off different bits in a bundle. Also, using "cds_thru" is not a real alias - it's an artificial alias (it actually netlists it as an iprobe in spectre) to cope with the situations where "patch" isn't supported (pin to pin aliases, or pin to global, or global to global). So you shouldn't need to use that either in this case.

    Regards,

    Andrew.

    • Post Points: 5
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Started by Glir at 14 Dec 2012 08:24 AM. Topic has 7 replies.