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 Continue after failed PSL assertions 

Last post Wed, Dec 12 2012 9:09 AM by wltr. 0 replies.
Started by wltr 12 Dec 2012 09:09 AM. Topic has 0 replies and 767 views
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  • Wed, Dec 12 2012 9:09 AM

    • wltr
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    • Joined on Wed, Dec 12 2012
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    Continue after failed PSL assertions Reply

    Hi!

    I am running a mixed-language simulation with irun. This includes PSL assertions in my VHDL code and SVA assertions in my SystemVerilog/UVM testbench.

    As the simulation runs in non-interactive mode on a cluster, I do not want the simulation to stop due to failed assertions. It rather should log it in the database and continue.

    But the simulation already stops on the first failed assertion. I was not able to find any configuration flag to force ncsim to continue automatically.

    Any hints would be highly appreciated.

    - Johannes 

     

    EDIT: Okay, sorry. I just found the problem. My own script prevented the simulation from continuing.  

    • Post Points: 5
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Started by wltr at 12 Dec 2012 09:09 AM. Topic has 0 replies.