I am designing a 4 layer board with some blind/buried vias.
So on “Manufacture -> NC -> NC Drill” I selected under “Drilling” the option
“By layer”. There are then generated 3 output files “file-1-2-np.drl”, “file-2-3-np.drl”and
In order to probe if everything was all right, I placed on
the board 4 mounting holes (the same symbol four times), but on the output
files 1-2 and 2-3 I got
While on the file 3-4 I got
So, one of the hole is only visible on the last layer; something
like a blind via but it is actually a passing though hole. I repeated the
process several times and the output was always the same. In fact, I discovered
that the last hole that I place on the PCB is the one that has the error on the
output files. If I choose the option of “Drilling” “Layer pair”, the output
file is correct.
Am I missing some configuration? Or maybe am I doing
something wrong? Any ideas?
I’m using Allegro PCB designer 16.5
Thank you very much.