Home > Community > Forums > Functional Verification > string macros in verilog AMS

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 string macros in verilog AMS 

Last post Mon, Nov 26 2012 8:18 AM by freitas. 0 replies.
Started by freitas 26 Nov 2012 08:18 AM. Topic has 0 replies and 803 views
Page 1 of 1 (1 items)
Sort Posts:
  • Mon, Nov 26 2012 8:18 AM

    • freitas
    • Top 500 Contributor
    • Joined on Wed, Nov 23 2011
    • Posts 29
    • Points 385
    string macros in verilog AMS Reply

    Hello, 

    Does anyone know how to define string  macros in Verilogams?

     

    Today I have to do the following:

    `define display_value(str, sig)  $display(“Value of signal %s is equal to %b”,  str, sig)

     If I place the following macro in my code

    `display_value(“mysignal”,mysignal);

     The compiler translates to

    $display(“Value of signal %s is equal to %b”,  “mysignal”, mysignal);

     Unfortunately, it forces me to duplicate information and maintain more code.

     Ideally I would like a macro that takes a single argument to create the signal name as well as its respective content.  Such as:

    `define display_value(sig)     ????????????????

    I wonder if there's a trick in verilogams to accomplish that. 

    Any ideas?

    Thanks,

    Art. 

    Filed under:
    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by freitas at 26 Nov 2012 08:18 AM. Topic has 0 replies.