Ya, I am not using QRC extraction. I have a verilog code (FSM basically). The output of this FSM is fed to a interpolator design that I have designed in cadence virtuoso. I have created a symbol out of the Verilog code. The outputs of this is goin to the interpolator which is designed using the standard gpdk045 library. I have created a top level in config mode and have integrated both the blocks. I am running using the simulator spectreverilog.
Everytime I try to run the simulation I get the following error shown below." End MS netlisting unsuccessful".
function simPostFunc redefined
Begin Incremental Netlisting Apr 21 00:09:28 2013
End netlisting Apr 21 00:09:28 2013
ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be corrupt
or may not be produced at all.
To generate correct netlist, fix the errors and re-netlist.
Begin Digital Netlisting: Apr 21 00:09:28 2013
Begin Incremental Netlisting Apr 21 00:09:29 2013
INFO (VLOGNET-60): The stimulus name mapped table will not be printed in the
"testfixture.verilog" file. To print the stimulus name mapped table, set
simVerilogPrintStimulusNameMappingTable = t either in CIW or the .simrc file
before invoking Verilog netlister.
INFO (VLOGNET-62): Database internal net names will be printed for floating instance ports. To prevent
them from being printed, set simVerilogProcessNullPorts = t either in CIW or
the .simrc file.
INFO (VLOGNET-64): All cellviews in the design will be printed in the Netlist Configuration list.
If you want to print only those cellviews that need to be re-netlisted in the
list, set simVerilogIncrementalNetlistConfigList = t either in CIW or the
INFO (VLOGNET-66): Module ports will be printed without the port ranges. If you have split busses
across module ports you may get an incorrect netlist. To print module ports
with the port ranges, set simVerilogDropPortRange = nil either in CIW or the
INFO (VLOGNET-68): The initial state of stimulus of all inout pins is set to "z". To get inout
pins with initial state of "0", set hnlVerilogIOInitStimulusStr = "0"
either in CIW or the .simrc file.
INFO (VLOGNET-117): Re-netlisting the entire design.
INFO (VLOGNET-120): Using connection by order (implicit connections) for all the stopping cells.
INFO (VLOGNET-126): ---------- Beginning netlist configuration information ----------
CELL NAME VIEW NAME NOTE
--------- --------- ----
state symbol *Stopping View*
inverter symbol *Stopping View*
---------- End of netlist configuration information ----------
INFO (VLOGNET-80): The library 'pro', cell 'IDIOT', and view 'config' has been netlisted successfully.
End netlisting Apr 21 00:09:29 2013
WARNING (OSSHNL-338): hnlMaxLineLength was set to 'nil. Resetting maximum line length value to 72
End MS Netlisting: Apr 21 00:09:29 2013
Please let me know what am I doing worng.Any help would be appreciated.
Thanks a lot!!