Extracted simulation ERROR (SFE-23): "input.scs" 17: c1 is an instance of an undefined model cmodel. 

Hi,

I am working on IC614 with the techonology IBM7RF. After extracting models from layout by Assura QRC, I tried to do the post-simulation with that extraction. However, a long list of errors (SFE-23) come out in ADE with Spectre simulator. I couldn't find "input.scs" in the model folder of the technology. Could anyone help to locate this file? Or other ideas to fix this error? Thanks in advance.

Best regards, 

The input.scs will be in the netlist directory used by ADE, not in the models from the technology. If you do Simulation->Netlist->Display in ADE it should show you the full path to the input.scs in the banner of the window.

Wherever ADE has it's project directory, on Setup->Simulator/Directory/Host  , you'll then find under there cellName/simulator/viewName/netlist - it will be in there.

Andrew.

Hi Andrew,

Thanks for your quick reply. I found "input.scs" in the directory you mentioned, and included it in ADE model libraries. Now turns to a new error:

     FATAL (SFE-879): Recursive file include or library call: `/home/zheng072/simulation/NOT_test/spectre/schematic/netlist/input.scs'.

Any idea about this error please?

Best regards,

bjbit 

Adding the netlist as a model file makes no sense at all. When you set up a model file, it will add include statements to the input.scs into the input.scs - and so you'll get a recursive include, as you've found - hardly surprising.

You didn't really give much detail as to your original problem, but presumably you need to include the model files from your technology/PDK - and exactly what you need to include is probably documented in the PDK documentation.

Regards,

Andrew.

Hi Andrew, 

I checked the content of input.scs and compared it with the extracted cellview. It seems that all undefined models come from analogLib. For example, undefined model "cmodel" is actually "pcapacitor" in the extraction. I don't know why the input.scs messes up the model name. Then I replaced the word "cmodel" with "pcapacitor" in input.scs, but same error said "pcapacitor" is also undefined model. At this point I am confused, since the schematic simulation with models from analogLib worked just fine, but fails to be defined here. Do I need to include a specific model file of analogLib in input.scs? So far I cannot find any .scs file in analogLib folder. Thanks for your time.

Best regards,

bjbit 

On the QRC Extraction form, go to the Netlisting tab, and ensure that you have Parasitic Capacitor Models and Parasitic Resistor Models set to either "Include As Comment" or "Do not include". You must have had it set to "Include Model".

That's useful if you want to provide a model to (say) scale the capacitance or resistance, but if you don't have such a model, you're best to leave them so that no model name is given. In this case, they'll get netlisted as resistor and capacitor in spectre.

Because I was reading on a handheld device I missed the end of the subject line - I might have realised that was what your problem was (your original posting was a bit confusing) - so my apologies for missing that.

Regards,

Andrew.

Hi Andrew,

Thanks a lot. The problem is solved now. You are right the setting in the netlisting tab is where caused the issue. Sorry about my confusing post at the beginning. I appreciate your helps.

Best regards,

bjbit 

Hi Andrew, 

         You have told to set to "Include Model"  on the QRC extraction form --> Netlisting tab to overcome the "recursive include error". How do I get to QRC Extraction form? Where can I find this ? Can you please let me know in detail. 

 The error I am getting is "Recursive file include or library call : ..... "    Please help 

Thanks 

I don't know what you're doing - the above example was specifically trying to solve a problem with QRC extraction - if you don't know where the QRC extraction form is, you're presumably not using QRC?

If your error is actually the recursive file include (which above was due to the person incorrectly trying to solve their original QRC issue), then it's because you have an include statement in spectre which is pointing back on itself. So please give the exact error message and also look at the top of the input.scs (the netlist you see in ADE when you do Simulation->Netlist->Display) and post any include statements here. That might help get to the bottom of what you've done wrong.

Kind Regards,

Andrew.

      Ya, I am not using QRC extraction. I have a verilog code (FSM basically). The output of this FSM is fed to a interpolator design that I have designed in cadence virtuoso. 

Everytime I try to run the simulation I get the following error shown below." End MS netlisting unsuccessful".

 function simPostFunc redefined

Begin Incremental Netlisting Apr 21 00:09:28 2013

End netlisting Apr 21 00:09:28 2013

ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be corrupt

 or may not be produced at all.

To generate correct netlist, fix the errors and re-netlist.

Begin Digital Netlisting: Apr 21 00:09:28 2013

Begin Incremental Netlisting Apr 21 00:09:29 2013

INFO (VLOGNET-60): The stimulus name mapped table will not be printed in the 

"testfixture.verilog" file. To print the stimulus name mapped table, set 

simVerilogPrintStimulusNameMappingTable = t either in CIW or the .simrc file 

before invoking Verilog netlister.

INFO (VLOGNET-62): Database internal net names will be printed for floating instance ports. To prevent 

them from being printed, set simVerilogProcessNullPorts = t either in CIW or 

the .simrc file.

INFO (VLOGNET-64): All cellviews in the design will be printed in the Netlist Configuration list. 

If you want to print only those cellviews that need to be re-netlisted in the 

list, set simVerilogIncrementalNetlistConfigList = t either in CIW or the 

.simrc file.

INFO (VLOGNET-66): Module ports will be printed without the port ranges. If you have split busses 

across module ports you may get an incorrect netlist. To print module ports 

with the port ranges, set simVerilogDropPortRange = nil either in CIW or the 

.simrc file.

INFO (VLOGNET-68): The initial state of stimulus of all inout pins is set to "z". To get inout 

pins with initial state of "0", set hnlVerilogIOInitStimulusStr = "0" 

either in CIW or the .simrc file.

INFO (VLOGNET-117): Re-netlisting the entire design.

INFO (VLOGNET-120): Using connection by order (implicit connections) for all the stopping cells.

INFO (VLOGNET-126): ---------- Beginning netlist configuration information ----------

CELL NAME                   VIEW NAME            NOTE             

---------                   ---------            ----             

state                       symbol               *Stopping View*  

inverter                    symbol               *Stopping View*  

IDIOT                       schematic                             

---------- End of netlist configuration information   ----------

INFO (VLOGNET-80): The library 'pro', cell 'IDIOT', and view 'config' has been netlisted successfully.

End netlisting Apr 21 00:09:29 2013

WARNING (OSSHNL-338): hnlMaxLineLength was set to 'nil. Resetting maximum line length value to 72 

characters.

End MS Netlisting: Apr 21 00:09:29 2013

      ...unsuccessful.

hiCaughtControlC

 Please let me know what am I doing worng.Any help would be appreciated.  

  Thanks a lot!! 

Ah, so it has absolutely nothing to do with the post you appended to. That's helpful...

Debugging this without seeing the data is going to be hard, so please contact customer support.

Regards,

Andrew.