very long bit pattern for vbit source 

Hello,

 I want to test a mixed signal design in cadence virtuoso 6.1.5 with spectre.

To verify the functionallity of the digital part a very long input sequence, thousands of bits, is necessary.

I tried using the vbit source. What is very usefull about this is that it is possible to adjust the voltage levels as well as the length of one bit. This makes it superior over the vpwl  at least for my application.

I found a helpful document that makes it possible to adjust the properties of vbit in a way that it is possible to insert a design variable for the data . Another document helped me to load a bitstream from a tex-file into this design variable inside ade-l. 

The problem is that this is only possible for short bitstreams. At least my bitstream is too long for such a proceeding.

Is there any other approach to solve this problem?

A stimulus file would also be very long/large...

regards Zitty 

Do you need a specific bit pattern, or would a psudeo random bit pattern be OK?

I created a verilog-A module which generates a PRBS 2^15 - 1 bit pattern.

Bit period can be set via a clock input signal, or with a verilog-a "timer" event generator.

Output amplitude can be set by a parameter, or by pwr/gnd input pins.

 Hope this is helpfull.

Tony

 Hey Tony,

I need a specific bit pattern to test the digital part of my design.

Verilog-A is a good idea but the code would become very large...

There are several ways to tackle this problem (that I can think of). One of the ways is to use spectre's ability to define patterns (see "spectre -h pattern"). If I create a file called (say) "patterns.scs" and include it in ADE as a model library:

 // my patterns

p1 pattern data="10111011011"
p2 pattern data="001100100101011"
p3 pattern data="1111100001110001100"

Then on the vbit source (or vsource with type set to "bit"), I can set the pattern as (say) "p1,p2,p3" or "p1,p2,p2,p3,p1" - whatever you like - and it will then use the sequence of predefined patterns from the include file.

The alternative is to use the "vector" file input. Look at Setup->Simulation Files and there's a Vector Files tab. You can add the path to vector files. For more details on the syntax, look at "spectre -h vector". The precise details of the format are in the Ultrasim User Guide (<MMSIMinstDir>/doc/UltraSim_Use/UltraSim_User.pdf) - in the chapter entitled "Digital Vector File Format"). This allows you to take a file of vectors (in different radixes) and connect to one or more signals in your circuit - replacing the need for sources on the schematic.

Regards,

Andrew.

 Dear Andrew,

Can the waveform generated from your second method have the rise time and fall time information intact ?

Kind Regards,

Not sure what you mean about having the rise time and fall time information intact, but you can specify the  rise and fall time (and various other signal characteristics) of the signals that are generated from the digital vectors. This is covered in the documentation that I mentioned earlier.

Regards,

Andrew

Well, I will see the doc.

Kind Regads,

 Dear Andrew,

Actually I am trying to change the pattern of the bit Source using the ocean script.

That is:-

In the 1st iteration of the run say the bit Source V2 will have "p1,p2,p3"

in the 2nd iteration of the run it will have "p2,p2,p1" and so on.

I tried to enter a parameter 'x' in the pattern data  tab of the V2 source so that I can change it in the ocean script but it is not taking it as a variable parameter.

Could you tell how it can be done so that I can change the pattern in the for loop ?

Kind Regards,

OK, this isn't entirely trivial. Follow these steps:

1. Copy the vbit source from analogLib into your own library, and call it vbitparam (make sure it's not called "vbit" as there is a check in the netlist procedure for being called vbit, which will defeat the next step)
2. Tools->CDF->Edit CDF and edit the "Base" CDF for the new vbitparam cell.
3. Go to the Simulation Information section, and select "spectre" as the simulator.
4. Remove "data" from the otherParameters section, and add it to the instParameters section
5. OK all the CDF editing forms
6. In your schematic, use the vbitparam component instead of vbit and set the "Pattern parameter data" parameter to be the name of the design variable you want.
7. In ADE or OCEAN, create a design variable with the same name as the design variable, and set the value to "p1,p2,p3" (with the quotes specified). In OCEAN this would be:
   desVar("myparam" "\"p1,p2,p3\"")

What the above is doing is getting the data parameter netlisted as a normal parameter (the netlist procedure that is usually used adds quotes around it, but in this case you don't want the quotes so that the value can be interpreted as a spectre parameter), and then you are ensuring the the netlist ends up with quotes around the parameter value. For example, here's my netlist:

simulator lang=spectre
global 0
parameters mypat="10010101"

// Library name: mylib
// Cell name: testbit
// View name: schematic
R0 (op 0) resistor r=1K
V0 (op 0) vsource val1=1 val0=0 data=mypat delay=0 rise=1n fall=1n \
        period=20n type=bit

Kind Regards,

Andrew.

 Dear Andrew,

Thanks a lot.

Just one mre thing:-

I am also using vsource-pwl for generating the clock waveform.

What exactly I am doing is that:-

I have captured the transient clk waveform  of another circuit and stored it in a text file ( time  amplitude) format. This clk is for one frequency.

I load the file in the vsource-pwl.

Similarly I have multiple .txt files for various frequrncies.

With the way anlogous to the way you have mentioned, can I change the file name in the loop by parameterizing it.

In other words I can run the sumulation for multiple frequency in a for loop.

Kind Regards,

Yes, do the same with the vpwlf source, and move the file parameter from otherParameters to instParameters.

Note, I didn't try this, but I believe it should work.

Andrew.