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 Glitch(Spike) in the output.. 

Last post Tue, Oct 30 2012 2:18 PM by Raki87. 2 replies.
Started by Raki87 28 Oct 2012 07:04 AM. Topic has 2 replies and 889 views
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  • Sun, Oct 28 2012 7:04 AM

    • Raki87
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    • Joined on Sun, Oct 28 2012
    • Posts 2
    • Points 25
    Glitch(Spike) in the output.. Reply
    Hello..I am new to cadence, I was trying to simulate the simple 'd' latch using cadence, but i noticed that there is a spike in the output going above my supply voltage and below the ground level( i have rise and fall time of clock and D input as 5 ns). When i increase the rise time and fall time of my clock(D) the glitch is reduced, but my fellow students who use the same version of the cadence, are getting the correct output even for rise , fall time of 5n sec. i get this glitch only when i simulate the schematic and not in layout simulation.. Is there anythin i missed in my transient analysis? because of this glitch my desired attributes are not met, please suggest me a way out..Thanks!
    • Post Points: 20
  • Mon, Oct 29 2012 7:11 AM

    • grasshopper
    • Top 25 Contributor
    • Joined on Thu, Jul 17 2008
    • Chelmsford, MA
    • Posts 241
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    Re: Glitch(Spike) in the output.. Reply

     Hi Raki87,

     can you please clarify what tools are you using? As far as RTL synthesis is concerned, most if not all synthesis tools in the market place do not perform any glitch mitigation so it is left to user to design circuity that is glitch tolerant. In fact, this is one of the reasons, why most synthesis tools are meant to be used for synchronous design and not asynchronous design. Glitches in such cases would lead to hazards, etc.

     gh-

    • Post Points: 20
  • Tue, Oct 30 2012 2:18 PM

    • Raki87
    • Not Ranked
    • Joined on Sun, Oct 28 2012
    • Posts 2
    • Points 25
    Re: Glitch(Spike) in the output.. Reply
    Hi,
    I am using Cadence spectre/Virtuoso for my simulation. I have a "D" latch driven by clock adn whenever the clock is transiting from high to low or low to high, there is a glitch in the output. If i increase the rise time of my clock the glitch will reduce, but my friend using the same tool, same version, same inputs works completely fine for him( even at low rise time of clock, (without any glitch). I wonder what might be wrong in my circuit.

    If i perform the post layout simulation of the same circuit it works fine, i have problem if i simulate my pre layout schematic. Please let me know if you need further info reg this.

    Thanks!
    Rakesh
    • Post Points: 5
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Started by Raki87 at 28 Oct 2012 07:04 AM. Topic has 2 replies.