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 Strange "out of memory" error during verilog import 

Last post Wed, Jan 2 2013 5:53 AM by Andrew Beckett. 1 replies.
Started by asimecs 09 Oct 2012 10:02 AM. Topic has 1 replies and 666 views
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  • Tue, Oct 9 2012 10:02 AM

    • asimecs
    • Not Ranked
    • Joined on Tue, Sep 11 2012
    • Posts 1
    • Points 20
    Strange "out of memory" error during verilog import Reply

    Hi,

     

    I am trying to save myself the pain of connect 300+ pins by importing a verilog file instead. But I got the following error. Can anyone shed some light on this? I cannot find anything on documentation nor Google.

     

     @(#)$CDS: ihdl.exe version 5.1.0 01/27/2011 00:14 (cicln04) $  Tue Oct  9 09:32:34 2012

    Verilog definition for module xyz was not found. Using lib 'blahblahblah' cell 'xyz' view 'symbol' as its symbol.
    Verilog definition for module abc  was not found. Using lib 'blahblahblah' cell 'abc' view 'symbol' as its symbol.

    Mismatch between existing view and view to be created for min_dig_sec
    Checked in symbol min_dig_sec
    Checked in functional view min_dig_sec. Expression on port found
    VerilogIn: *F,45: Out of memory. Cannot allocate space.Exiting.
    End of Logfile.

    • Post Points: 20
  • Wed, Jan 2 2013 5:53 AM

    Re: Strange "out of memory" error during verilog import Reply

    The size of what you're trying to import doesn't sound excessive. Please contact customer support (not that we'll be able to fix it in IC5141 since IC5141 has no more hotfixes (the release came out over 8 years ago) - you might want to try using the latest IC5141 hotfix first).

    Andrew.

    • Post Points: 5
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Started by asimecs at 09 Oct 2012 10:02 AM. Topic has 1 replies.