I am trying to save myself the pain of connect 300+ pins by importing a verilog file instead. But I got the following error. Can anyone shed some light on this? I cannot find anything on documentation nor Google.
@(#)$CDS: ihdl.exe version 5.1.0 01/27/2011 00:14 (cicln04) $ Tue Oct 9 09:32:34 2012
Verilog definition for module xyz was not found. Using lib 'blahblahblah' cell 'xyz' view 'symbol' as its symbol.
Verilog definition for module abc was not found. Using lib 'blahblahblah' cell 'abc' view 'symbol' as its symbol.
Mismatch between existing view and view to be created for min_dig_sec
Checked in symbol min_dig_sec
Checked in functional view min_dig_sec. Expression on port found
VerilogIn: *F,45: Out of memory. Cannot allocate space.Exiting.
End of Logfile.