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 simulating hierarchical VHDL design using AMS 

Last post Wed, Oct 3 2012 7:08 AM by Hesham2012. 2 replies.
Started by Hesham2012 30 Sep 2012 07:44 AM. Topic has 2 replies and 1570 views
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  • Sun, Sep 30 2012 7:44 AM

    • Hesham2012
    • Not Ranked
    • Joined on Sun, Apr 17 2011
    • Thuwal, Saudi Arabia
    • Posts 8
    • Points 55
    simulating hierarchical VHDL design using AMS Reply

    Hi

     

    I am trying to simulate a mixed signal design. The digital part is a hierarchical VHDL design. The digital desing is simulating fine with incisive.

    But when I tried ams from whitin virtuoso I received all kinds of errors. I tried a flat design and it works fine. But the errors are for the heirarchical one. An example of instatnce definition I use is below:

    coarse_cntr: entity work.reg

    generic map(

    WIDTH => COARSE_REG_WIDTH

    )

    port map(

    arst => arst_i,

    clk => clk_coarse_q,

    en => en_coarse_cntr,

    srst => '0',

    load => '0',

    incr => '1',

    shift => '0',

    sdi => '0',

    di => (others => '0'),

    sdo_q => open,

    do_q => coarse_cnt_q_i

    );

    I added hdl.var file and added the work library in cds.lib as explained in the help, but I still get work library error:

    WRKBAD: logical library name WORK is bound to a bad library name WORK

    When I remove hdl.var file, I still get a lot of errors due to the statement "entity work.name"

    I also noted that the hierarchy is sometimes capture by HED and sometimes not. How can I force compilation of the top module for heirarchy to appear in HED?

    Please help if u've done hierarchical VHDL simulation before using AMS 

    • Post Points: 5
  • Tue, Oct 2 2012 4:47 AM

    • Hesham2012
    • Not Ranked
    • Joined on Sun, Apr 17 2011
    • Thuwal, Saudi Arabia
    • Posts 8
    • Points 55
    Re: simulating hierarchical VHDL design using AMS Reply

    The solution is below! 

    I am using IC6.1.4 and IUS8.2 

    Here is the flow after working around the bugs with cadence support

    • Create proj folder
      • Created a dir in the proj dir called “work”
      • Create cds.lib and add

    SOFTINCLUDE $AMSHOME/tools/inca/files/IEEE_vhdlams/cds.lib

    SOFTINCLUDE $CDSHOME/share/cdssetup/dfII/cds.lib

    DEFINE work ./work

    •  
      • Create hdl.var and add

    SOFTINCLUDE $AMSHOME /tools.lnx86/inca/files/hdl.var

    DEFINE WORK work

     

    • Start virtuoso
    • Import the vhdl files from CIW (note that when you change schmematic to vhdl, modules with generics fail. Also modules with generics will not have symbols).
    • Alternatively, you can compile them from terminal, and they will directly appear in lib manager using >> ncvhdl –messages -smartorder -work work -v93 file1.vhd file2.vhd
    • You then create a tb schem and create config view. Config view will not detect the hierarchy because files are not compiled.
      • You can compile them using ncvhdl as in the previous step
        • But you will need to update the text views in lib manager by opening and closing them! Otherwise you will receive this error

    \o ERROR (OSSHNL-381): Missing or corrupt .oa file in cellview 'work/async_div4/rtl'. The OSS netlister can only
    \o process cellviews that have a valid .oa file. This file can be created by
    \o either importing the cellview using tools like 'Verilog In' or 'VHDL IN', or by
    \o opening and writing the text file in the Library Manager

    •  
      • Use Tools -> AMS -> netilist from CIW and choose the vhdl configuration (rtl view). Repeat for all modules.

    • Now in HED you will see the hierarchy.
    • The problem now is that if you create adexl test and attach it to the config view, you will (sometimes) receive the strange message:

    *Error* error: basic_string::_S_construct NULL not valid – nil

    • The work around is
      • Use ADEL instead of ADEXL, or
      • Remove the vhdl block from the schem, create adexl, then add the block again! A smarter way of doing this is adding stop point to the top module in HED, creating and setting adexl test (ams/OSS/connrules), then remove the stop point again!
    You can simulate now! (Alhamd le AllahJ)
    • Post Points: 5
  • Wed, Oct 3 2012 7:08 AM

    • Hesham2012
    • Not Ranked
    • Joined on Sun, Apr 17 2011
    • Thuwal, Saudi Arabia
    • Posts 8
    • Points 55
    Re: simulating hierarchical VHDL design using AMS Reply
    • Regretfully, the error will back every time you start adexl! For a permanent fix, use in CIW:

    (envSetVal "adexl.gui" "disableConstraintsRead" 'boolean t)

     

    It turned out to be a bug with VHDL generate statement for IC6.1.4 

    • Post Points: 5
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Started by Hesham2012 at 30 Sep 2012 07:44 AM. Topic has 2 replies.