Home > Community > Forums > Functional Verification > Looking for help with System Verilog in AMS

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Looking for help with System Verilog in AMS 

Last post Sat, Sep 15 2012 10:39 AM by Shalom B. 12 replies.
Started by JRAHildebrand 10 Sep 2012 04:52 PM. Topic has 12 replies and 3035 views
Page 1 of 1 (13 items)
Sort Posts:
  • Mon, Sep 10 2012 4:52 PM

    Looking for help with System Verilog in AMS Reply

    I've generated a netlist for a testcase and get the following error in the irun.log:

    Elaborating the design hierarchy:

    bias i_bias ( .ibias(ibias[3:0]), .vdd(vdd), .vss(vss), .en(en[0]));

                                             |

    ncelab: *E,CUINFI (./netlist.vams,39|41): An interface declaration must be connected to an interface (test_top.i_top).

       Analog vdd, vss;

                |

    ncelab: *E,CUIMBC (./development/SYS_VLOG_ANA_TEST/bias_verilog.sv,42|12): An interface port declaration must be connected (test_top.i_top.i_bias).

    bias i_bias ( .ibias(ibias[3:0]), .vdd(vdd), .vss(vss), .en(en[0]));

                                                        |

    ncelab: *E,CUINFI (./netlist.vams,39|52): An interface declaration must be connected to an interface (test_top.i_top).

       Analog vdd, vss;

                     |

    ncelab: *E,CUIMBC (./development/SYS_VLOG_ANA_TEST/bias_verilog.sv,42|17): An interface port declaration must be connected (test_top.i_top.i_bias). 

     

    That goes on for a while and there are a number of them.  So, the question is how do I connect the port declaration?  Here's the file referenced:

     import ADMS_signals_pkg::*;

     

    module bias (

                  vdd,

                  vss,

                  en,

                  ibias

                 );

       

    `include "parameters.svh"

     

       Analog vdd, vss;

       Analog ibias[3:0];

       input wire en;

         

       Amps                 iout[3:0];

       integer              vdd_ok;

       integer              vss_ok;

       integer              supplies_ok;

       event                started;

    //   Driver vdd_d         = new(vdd);

    //   Driver vss_d         = new(vss);

       ISource ibias_src[3:0];

       initial begin

          foreach (ibias_src[i]) 

            begin

               ibias_src[i]=new(ibias[i]);

            end

          @(en == 1'b1 && supplies_ok == TRUE);

          #100 -> started;

       end

     

    //   Driver ibias_d = new(ibias[1]);

    //   Driver ibias_d = new(ibias[2]);

    //   Driver ibias_d = new(ibias[3]);

     

       always @(vdd.changed)

         begin

            if (vdd.v < VDD_MIN)

              vdd_ok = FALSE;

            else if (vdd.v > VDD_MAX)

              vdd_ok = FALSE;

            else

              vdd_ok = TRUE;

         end

                

       always @(vss.changed)

         begin

            if (vss.v < VSS_MIN)

              vss_ok = FALSE;

            else if (vss.v > VSS_MAX)

              vss_ok = FALSE;

            else

              vss_ok = TRUE;

         end

     

       always @(vdd_ok, vss_ok)

         begin

            if (vdd_ok == TRUE && vss_ok == TRUE)

              supplies_ok = TRUE;

            else

              supplies_ok = FALSE;

         end

     

       initial iout[0] = -IBIAS_TYP;

       initial iout[1] = -IBIAS_TYP;

       initial iout[2] = -IBIAS_TYP;

       initial iout[3] = -IBIAS_TYP;

     

       always @(started,en)

         begin

            foreach (ibias_src[i])

              if ( en==1'b1 && supplies_ok==TRUE)     

                ibias_src[i].seti(iout[i]);

              else

                ibias_src[i].seti(0.0);

         end

    endmodule // bias 

    Filed under:
    • Post Points: 20
  • Tue, Sep 11 2012 7:14 AM

    • Shalom B
    • Top 200 Contributor
    • Joined on Mon, Jul 14 2008
    • Jerusalem, 00-IL
    • Posts 42
    • Points 585
    Re: Looking for help with System Verilog in AMS Reply

    At least part of the problem is that when irun reads a file that it identifies as an SV file by its extension, like bias_verilog.sv, then when it sees a type that is undefined from its point of view, such as "analog", it assumes that it is an interface type, which is not the case here, and then it gets all confused.

     Shalom

    Shalom.Bresticker@intel.com
    • Post Points: 20
  • Tue, Sep 11 2012 9:42 AM

    Re: Looking for help with System Verilog in AMS Reply

    I do have an include file which gets included when it creates the netlist.sv called ADMS_signals_pkg.sv.  Since the bias_verilog.sv is included (with the -v in the AMS Options form) the definition for the bias module is in the netlist.sv, too.  So it should get the Analog definition.  Or am I doing something wrong with that kind of setup? 

    In ADMS_signals_pkg.sv I have the following: 

      // Parent class for Analog connections

      virtual class Connections ;  // Connections to Analog nets

        virtual interface Analog ownerNet;

        protected Amps inet;     // Branch current from the net

        function new(virtual Analog owner = null);

          ownerNet = owner;

        endfunction

        task set() ; // Sets connection values and then calls net resolution

        endtask

        virtual function Amps getinet() ; // Get net branch current

        endfunction

        function Watts power() ; // get power disipated(-) or sourced(+) from the connection

          return ownerNet.v*inet ;

        endfunction

      endclass : Connections

     

    • Post Points: 20
  • Tue, Sep 11 2012 2:24 PM

    • tpylant
    • Top 50 Contributor
    • Joined on Fri, Jul 11 2008
    • Austin, TX
    • Posts 135
    • Points 2,030
    Re: Looking for help with System Verilog in AMS Reply
    It would be helpful to see the top of the log file that shows all the options being passed to irun.

    Tim
    • Post Points: 20
  • Tue, Sep 11 2012 2:36 PM

    Re: Looking for help with System Verilog in AMS Reply
    Thanks for all the help, guys.  Here's the head of the irun.log:
     
    irun: 11.10-s062: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
    TOOL: irun 11.10-s062: Started on Sep 11, 2012 at 09:30:37 PDT
    irun
    -f irunArgs
    -UNBUFFERED
    -errormax 50
    -status
    -nowarn DLNOHV
    -sysv_ext .sv
    -v93
    -incdir ./development/SYS_VLOG_ANA_TEST/sv_resolution/
    -timescale 1ns/1ns
    -vtimescale 1ns/1ns
    -discipline logic
    -delay_mode None
    -novitalaccl
    -access r
    -noparamerr
    -amspartinfo ../psf/partition.info
    -modelincdir ./development/SYS_VLOG_ANA_TEST/sv_resolution/
    -analogcontrol ./amsControlSpectre.scs
    -input ./probe.tcl
    -run
    -exit
    -ncsimargs "+amsrawdir ../psf"
    -simcompatible_ams spectre
    -name test_top:config
    ./netlist.vams
    -f ./textInputs
    ./development/SYS_VLOG_ANA_TEST/sv_resolution/test_system_verilog/vga/systemVerilog/verilog.sv
    ./development/SYS_VLOG_ANA_TEST/sv_resolution/test_system_verilog/dig/systemVerilog/verilog.sv
    ./development/SYS_VLOG_ANA_TEST/sv_resolution/test_system_verilog/dac/systemVerilog/verilog.sv
    ./development/SYS_VLOG_ANA_TEST/sv_resolution/test_system_verilog/vco/systemVerilog/verilog.sv
    ./development/SYS_VLOG_ANA_TEST/sv_resolution/test_system_verilog/adc/systemVerilog/verilog.sv
    ./development/SYS_VLOG_ANA_TEST/sv_resolution/test_system_verilog/stim/systemVerilog/verilog.sv
    ./development/SYS_VLOG_ANA_TEST/sv_resolution/test_system_verilog/source/systemVerilog/verilog.sv
    -v ./development/SYS_VLOG_ANA_TEST/bias_verilog.sv
    ./cds_globals.vams
    -l ../psf/irun.log
    file: ./development/SYS_VLOG_ANA_TEST/bias_verilog.sv
    package bias_verilog.ADMS_signals_pkg:sv
    errors: 0, warnings: 0
    • Post Points: 20
  • Tue, Sep 11 2012 2:50 PM

    • tpylant
    • Top 50 Contributor
    • Joined on Fri, Jul 11 2008
    • Austin, TX
    • Posts 135
    • Points 2,030
    Re: Looking for help with System Verilog in AMS Reply
    Try taking off the '-v' and just call out the file directly.

    Tim
    • Post Points: 20
  • Tue, Sep 11 2012 3:26 PM

    Re: Looking for help with System Verilog in AMS Reply

    I don't put the -v in, ADE appears to do that when I hit the netlist and run button.

    The file is added via the "Library Files" line in the ADE-L -> Simulation -> Options -> AMS Simulator

    The bias_verilog.sv file is just one that gives me the error, too.  Others listed in the -f also give the same problem (vga, dac, vco, adc, source specifically).  

    • Post Points: 20
  • Wed, Sep 12 2012 12:26 AM

    • Shalom B
    • Top 200 Contributor
    • Joined on Mon, Jul 14 2008
    • Jerusalem, 00-IL
    • Posts 42
    • Points 585
    Re: Looking for help with System Verilog in AMS Reply

    Where is the type 'Analog' (with uppercase A) declared?

     

    Shalom

    Shalom.Bresticker@intel.com
    • Post Points: 20
  • Wed, Sep 12 2012 8:15 AM

    Re: Looking for help with System Verilog in AMS Reply

    In an included file.  Here's the top of the file with the Analog portion.

    package ADMS_signals_pkg;

      typedef enum {x,ok} Astatus ;

      typedef real Volts;

      typedef real Amps;

      typedef real Ohms;

      typedef real Mhos;

      typedef real Watts;

      parameter Ohms open_circuit = 1.0e100;

      // unit multipliers

      `define u *1e-6  //micro

      `define m *1e-3  //milli

      `define n *1e-9  //nano

      `define p *1e-12 //pico

      `define f *1e-15 //femto

      `define K *1e+3  //kilo

      `define M *1e+6  //mega

      `define G *1e+9  //giga

     

      // Parent class for Analog connections

      virtual class Connections ;  // Connections to Analog nets

        virtual interface Analog ownerNet;

        protected Amps inet;     // Branch current from the net

        function new(virtual Analog owner = null);

          ownerNet = owner;

        endfunction

        task set() ; // Sets connection values and then calls net resolution

        endtask

        virtual function Amps getinet() ; // Get net branch current

        endfunction

        function Watts power() ; // get power disipated(-) or sourced(+) from the connection

          return ownerNet.v*inet ;

        endfunction

      endclass : Connections

     

    • Post Points: 5
  • Thu, Sep 13 2012 4:29 PM

    Re: Looking for help with System Verilog in AMS Reply

    I updated my version of Incisiv from 11.10.062 to 12.10.005. It gave better error messages and now I can get through compilation but it still generates errors in Elaboration. Here is a piece of the irun.log:

    Elaborating the design hierarchy:

    bias i_bias ( .vdd(vdd), .vss(vss), .en(en[0]), .ibias(ibias) );

                                 |

    ncelab: *E,CUINFI (./simulation/test_top/ams/config/netlist/netlist.vams,39|21): An interface declaration must be connected to an interface (test_top.i_top).

    Analog vdd, vss;

                   |

    ncelab: *E,CUIMBC (../bias_verilog.sv,42|12): An interface port declaration must be connected (test_top.i_top.i_bias).

    All the errors seem to be with the vdd, vss, ibias which are declared Analog (as per the previous post I did with the section where it has the interface declaration). Here is now the netlist.ams calls this block:

    bias i_bias ( .vdd(vdd), .vss(vss), .en(en[0]), .ibias(ibias) );

    So again I'm stumped as to why it appears to be connected and the elaboration says it's not. Jeff

    • Post Points: 20
  • Thu, Sep 13 2012 7:27 PM

    • Shalom B
    • Top 200 Contributor
    • Joined on Mon, Jul 14 2008
    • Jerusalem, 00-IL
    • Posts 42
    • Points 585
    Re: Looking for help with System Verilog in AMS Reply

    I still did not see a declaration of the type Analog.

     All I saw were virtual interface declarations using Analog as the interface type.

     That already implies implies that Analog is an interface type.

    Shalom

    Shalom.Bresticker@intel.com
    • Post Points: 20
  • Fri, Sep 14 2012 8:29 AM

    Re: Looking for help with System Verilog in AMS Reply

    Shalom: Would it be ok if I sent you email with the files directly?  I don't see any way to attach files to a message in the forum.

     

    Thanks,

    Jeff 

    • Post Points: 20
  • Sat, Sep 15 2012 10:39 AM

    • Shalom B
    • Top 200 Contributor
    • Joined on Mon, Jul 14 2008
    • Jerusalem, 00-IL
    • Posts 42
    • Points 585
    Re: Looking for help with System Verilog in AMS Reply
    Shalom.Bresticker@intel.com
    • Post Points: 5
Page 1 of 1 (13 items)
Sort Posts:
Started by JRAHildebrand at 10 Sep 2012 04:52 PM. Topic has 12 replies.