I have a problem generating SDF file in encounter. The problem is that the generated SDF file only includes delay information for the interconnects but not the gates. Here is how I generated the SDF file:
I have a standard cell library containing all the required cellviews (i.e. schematic, symbol, layout, abstract), Also I have the LEF file for the mentioned standard cell library. I imported a verilog netlist beside the LEF file in encounter, placed & routed the design, and finally generated the SDF file.
After opening the SDF in an editor I only see delay information for the interconnects. I don't understand why the gates input to output path delays are missing in the generated SDF file.
I would appreciate if somebody could tell me what I'm missing.