Home > Community > Forums > Functional Verification > Using Eplanner with UVM

Email
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Using Eplanner with UVM 

Last post Tue, Aug 14 2012 2:01 AM by rdalibor. 2 replies.
Started by rdalibor 13 Aug 2012 10:21 AM. Topic has 2 replies.
Page 1 of 1 (3 items)
Sort Posts:

  • Mon, Aug 13 2012 10:21 AM

    • rdalibor
    • Not Ranked
    • Joined on Mon, Aug 13 2012
    • Posts 2
    • Points 25
    Using Eplanner with UVM Reply
    I am trying to implement checkers in my UVM environment from my vPlan and to map them in Eplanner. However, in the Eplanner I can only see the checks that I implemented as assertions in interfaces but not the checkers I implemented as assertions in my UVM monitor. Could anyone explain me how should I implement checkers in my UVM monitor in order to see them in Eplanner in order to be able to map them.
    Filed under: ,
    • Post Points: 20

  • Tue, Aug 14 2012 1:07 AM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
    • Posts 238
    • Points 3,750
    Re: Using Eplanner with UVM Reply

    I'm assuming that you're referring to UVM-SV since you mention interfaces. If you'd been talking UVM-e it's easy, just enable coverage of checks in Specman using the "collect_checks_expects" option.

    For SV, Incisive doesn't currently collect coverage of immediate assertions in classes, though it's something that we're planning to do. As such, it's not possible for Enterprise Planner to show you the SV assertions, since the simulator didn't put them into the coverage model.

    I recently wrote an application note that shows a fairly straight-forward way round the limitation. You can read it here and see the example code: http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11784374 

    Steve. 

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    Filed under:
    • Post Points: 20

  • Tue, Aug 14 2012 2:01 AM

    • rdalibor
    • Not Ranked
    • Joined on Mon, Aug 13 2012
    • Posts 2
    • Points 25
    Re: Using Eplanner with UVM Reply

    Hi Steve.

    Yes I was referring to UVM-SV. I implemented your way round the limitation and I was able to map check in the Eplanner. My way round the limitation was to introduce an interface with the signals that are not actually connected to DUT but just used as auxiliary signals which are set from the monitor and then I implemented assertions on those signals in that interface.

    Thank you,

    Dalibor
    • Post Points: 5
Page 1 of 1 (3 items)
Sort Posts:
Started by rdalibor at 13 Aug 2012 10:21 AM. Topic has 2 replies.