I am trying to do P&R on a design, but it seems that all of my antenna diodes and filler cells cause short errors to the vdd and gnd rails in Encounter using Verify Geometry after placement.
The filler cell is only two metal rails in the same locations as our standard cells (labelled correctly for abstract generator) and nwell for continuity. We have multiple sizes of these, and these do not overlap any cells due to our sizing.
The antenna diode cell is the filler cell with a PMOS with D and S tied to vdd and a NMOS with G and S tied to ground and D to its input for the necessary gate gonnections.
We are using Abstract Generator to abstract our cells, and no errors are being produced during this process. The abstracts, extracts, and pins views look correct, based on versions of our standard cells. The vdd and gnd pins are showing in the pins view, and they do have the same name as all of our other cells.
Could something be wrong in the abstract generation, or is there a setting I should use in Encounter to prevent these cells from being checked for these errors?