I'm currently working with Cadence 16.5 and I would like to add an interlayer spacing constraint for two adjacent layers, in order to prevent interlayer crosstalk between differential pairs.
I spent some hours looking for a solution, and I found this post : http://www.cadence.com/Community/forums/p/18113/1251634.aspx where Icanx2 talks about “PCB Interlayer Clearance Rule”.
I searched into Cadence's help and found a procedure to set interlayer spacing rule, but the problem is that the first step is : Choose Rules - PCB - Interlayer - By Layer Pair, but I couldn't find this menu anywhere in the GUI...
I also found a command line to set this parameter : "rule PCB (inter_layer_clearance 1.2 (layer_pair cc via))", but when I use the same command line with the layer names corresponding to my layout, Allegro tells me that the command couldn't be found...
If someone already worked on interlayer nets spacing and knows how to set a rule generating a DRC this would be really helpful.
Thank you very much,
Have a nice day.