After spending some time to setup a mixed-signal simulation, I reached a point where I can no longer increase the simulation speed. The chip core is referencing behavioral VHDL and a majority of the analog modules are represented by Verilog-A code. I am simulating using irun. I was wondering it if would be possible to see which part of the IC is slowing down my simulation? I have also noticed that when I represent some modules in Verilog-A, it can slow down the simulation. I'd like to have a better understanding of which modules are doing what.
I am using mmsim710 and ius82.