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 Practical limit to the number of elements in a vector port in VerilogA 

Last post Mon, Jun 18 2012 9:50 AM by Andrew Beckett. 1 replies.
Started by Herge 18 Jun 2012 09:45 AM. Topic has 1 replies and 765 views
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  • Mon, Jun 18 2012 9:45 AM

    • Herge
    • Top 500 Contributor
    • Joined on Fri, May 8 2009
    • Oudenaarde, Belgium
    • Posts 17
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    Practical limit to the number of elements in a vector port in VerilogA Reply

    Hello,

    With the nice support for port vectors, parameter arrays and FOR loops, one can write module code for a theoretically unlimited number of ports. I have built a module where the number of ports is parametrized with a pre-processor variable.

    I am wondering what are the practical limits to the number of ports of a verilogA module ?
    What is the limit to the number of iterations in FOR loops ?

    My module is meant to simulate parasitic bipolar interactions in the substrate. In our chips we easily have several 100's of junctions. We've set ourselves a target to be able to handle 1000 junctions. This means 2 port vectors with 1000 elements (plus an additional 1000 internal nodes).

     We have already checked that a mesh with >10k instances of 4-port devices generated by the same module converges smoothly in SPECTRE.

    We have not yet checked that an instance of the 2K ports module works... Should we expect (bad) surprises ?

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    • Post Points: 20
  • Mon, Jun 18 2012 9:50 AM

    Re: Practical limit to the number of elements in a vector port in VerilogA Reply

    I have no idea. I doubt there's any simple or hard number - it's more likely that you'll hit performance limits in some situation, and that's going to be very dependent on precisely what you're doing.

    Andrew.

    • Post Points: 5
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Started by Herge at 18 Jun 2012 09:45 AM. Topic has 1 replies.