With the nice support for port vectors, parameter arrays and FOR loops, one can write module code for a theoretically unlimited number of ports. I have built a module where the number of ports is parametrized with a pre-processor variable.
I am wondering what are the practical limits to the number of ports of a verilogA module ?
What is the limit to the number of iterations in FOR loops ?
My module is meant to simulate parasitic bipolar interactions in the substrate. In our chips we easily have several 100's of junctions. We've set ourselves a target to be able to handle 1000 junctions. This means 2 port vectors with 1000 elements (plus an additional 1000 internal nodes).
We have already checked that a mesh with >10k instances of 4-port devices generated by the same module converges smoothly in SPECTRE.
We have not yet checked that an instance of the 2K ports module works... Should we expect (bad) surprises ?