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 How will I do a HAL Hdl analysis on vhdl design? 

Last post Tue, Jun 26 2012 6:23 AM by TAM1. 7 replies.
Started by sonam20 18 Jun 2012 02:55 AM. Topic has 7 replies and 5469 views
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  • Mon, Jun 18 2012 2:55 AM

    • sonam20
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    How will I do a HAL Hdl analysis on vhdl design? Reply

    I want to do a HAL analysis on VHDL design.What are the procedure and steps for that?/

    Please tell me

    thanks,

    Shivani

    • Post Points: 20
  • Mon, Jun 18 2012 4:38 AM

    • StephenH
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    Re: How will I do a HAL Hdl analysis on vhdl design? Reply

    Hi Shivani.

    If you compile your design with "irun" already then you can just add the "-hal" switch, then use the "ncbrowse" tool to review the lint messages via a GUI.

    Alternatively if you use ncvhdl/ncelab/ncsim, then after elaboration you can invoke "hal" and pass the snapshot name on the command line to HAL.

     

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
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    • Post Points: 20
  • Mon, Jun 18 2012 10:53 PM

    • sonam20
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    Re: How will I do a HAL Hdl analysis on vhdl design? Reply

     Hello,

    apply command "nclaunch" 

    select a design 

    select all vhd files in selcted design and press ncvhdl option .

    After this it give various errors .. How to resolve that?

    How to elaborate particlar design?

    thanks

    Shivani

     

     

    • Post Points: 20
  • Mon, Jun 18 2012 11:39 PM

    • sonam20
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    Re: How will I do a HAL Hdl analysis on vhdl design? Reply

     How to get sanpshot of elaborated design.??

    • Post Points: 5
  • Tue, Jun 19 2012 3:39 AM

    • StephenH
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    Re: How will I do a HAL Hdl analysis on vhdl design? Reply

    Shivani,

    Without seeing your compilation log there is no way to know what those VHDL errors are, nor can we guide you to resolve those unknown errors. I would recommend talking to one of your colleagues to get the required compilation order for the files, as well as any specific switches like VHDL-93 options etc.

    Alternatvely you could post the log file here, or go to http://support.cadence.com/ and file a service request asking for help to run HAL.

    Steve.

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    • Post Points: 20
  • Mon, Jun 25 2012 11:28 PM

    • sonam20
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    Re: How will I do a HAL Hdl analysis on vhdl design? Reply

    HI,

    I found these type of error after compilation. Please tell me how to resolve them.

     ncvhdl_p: *E,LIBNOM (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,35|18): logical library name must be mapped to design library [11.2].
    USE DESIGN.BB_PKG.All;
             |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,38|9): identifier (DESIGN) is not declared [10.3].
    USE DESIGN.WB_INTERNAL_PKG.ALL;
             |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,39|9): identifier (DESIGN) is not declared [10.3].
    USE DESIGN.COMMON_PKG.ALL;
             |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,40|9): identifier (DESIGN) is not declared [10.3].
        P_SLAVE_BASE_ADDR : slave_addr_a_t(0 TO P_NUM_SLAVES-1)      := (((x"0000"),(x"0280"),(x"0000")),  --! Specifies base address of each slaves
                                         |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,48|37): identifier (SLAVE_ADDR_A_T) is not declared [10.3].
        P_SLAVE_ADDR_SIZE : slave_addr_a_t(0 TO P_NUM_SLAVES-1)      := (((x"007f"),(x"027f"),(x"0000")),     --! Specifies the address size of each slave   
                                         |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,52|37): identifier (SLAVE_ADDR_A_T) is not declared [10.3].
        P_SLAVE_ADDR_CH   : slave_addr_ch_a_t(0 TO P_NUM_SLAVES-1)   := (('1','1','0'),     --! Specifies the active address part of each slave   
                                            |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,56|40): identifier (SLAVE_ADDR_CH_A_T) is not declared [10.3].
        P_SHARE_PRIO      : int_vector(0 TO P_NUM_MASTERS-1)         := (1,2,3,4,5)         --! Priority of master
                                     |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,60|33): identifier (INT_VECTOR) is not declared [10.3].
        wbm_i       : OUT wbm_i_a_type(0 TO P_NUM_MASTERS-1);  --! Wishbone master input interface array
                                     |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,71|33): identifier (WBM_I_A_TYPE) is not declared [10.3].
        wbm_o       : IN  wbm_o_a_type(0 TO P_NUM_MASTERS-1);  --! Wishbone master output interface array
                                     |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,72|33): identifier (WBM_O_A_TYPE) is not declared [10.3].
        wbs_o       : IN  wbs_o_a_type(0 TO P_NUM_SLAVES-1);   --! Wishbone slave output interface array
                                     |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,76|33): identifier (WBS_O_A_TYPE) is not declared [10.3].
        wbs_i       : OUT wbs_i_a_type(0 TO P_NUM_SLAVES-1)    --! Wishbone slave input interface array
                                     |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,77|33): identifier (WBS_I_A_TYPE) is not declared [10.3].
    ARCHITECTURE rtl OF intercon IS
                               |
    ncvhdl_p: *E,ENNOFN (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,82|27): Intermediate file for entity 'INTERCON' could not be loaded, entity may require re-analysis.
    LIBRARY design;
                 |
    ncvhdl_p: *E,LIBNOM (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,39|13): logical library name must be mapped to design library [11.2].
    USE design.bb_pkg.ALL;
             |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,40|9): identifier (DESIGN) is not declared [10.3].
    USE design.common_pkg.ALL;
             |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,41|9): identifier (DESIGN) is not declared [10.3].
        dm_in         : IN dm_in_a_t(0 TO P_NUM_REG_MAP-1);   --! Number of elements = no. of register maps    
                                   |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,50|31): identifier (DM_IN_A_T) is not declared [10.3].
        reg_wbs_i     : IN  wbs_i_type;
                                     |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,54|33): identifier (WBS_I_TYPE) is not declared [10.3].
        dm_out        : OUT  dm_out_t;   
                                    |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,58|32): identifier (DM_OUT_T) is not declared [10.3].
        reg_wbs_o     : OUT wbs_o_type
                                     |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,62|33): identifier (WBS_O_TYPE) is not declared [10.3].
    ARCHITECTURE rtl OF wb_dm_bridge IS
                                   |
    ncvhdl_p: *E,ENNOFN (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,68|31): Intermediate file for entity 'WB_DM_BRIDGE' could not be loaded, entity may require re-analysis.
      Concatenation: FOR i IN P_NUM_REG_MAP DOWNTO 1 GENERATE BEGIN
                                                              |
    ncvhdl_p: *E,EXPEND (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,83|58): expecting the reserved word 'END' [9.7].
    END ARCHITECTURE rtl;
                   |
    ncvhdl_p: *E,OPARCH (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_dm_bridge.vhd,134|15): Optional end architecture is only allowed in 93[1.2].
    ncvhdl_p: Memory Usage - 8.4M program + 4.9M data = 13.2M total
    ncvhdl: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.1s, 24.0% cpu)

    • Post Points: 35
  • Mon, Jun 25 2012 11:43 PM

    • Brodov Dmitriy
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    Re: How will I do a HAL Hdl analysis on vhdl design? Reply

    Hello,

    You can use cadence quick help for more explanation: nchelp ncvhdl_p LIBNOM 

     

    ncvhdl_p/LIBNOM =

            The logical library name indicated is not mapped to a design library.

            Section [11.2] of LRM [87 & 93].  A user option file entry of the form:

                    L: directory

            must be present for each logical library name L.

     

    • Post Points: 5
  • Tue, Jun 26 2012 6:23 AM

    • TAM1
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    Re: How will I do a HAL Hdl analysis on vhdl design? Reply

    ncvhdl_p: *E,LIBNOM (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,35|18): logical library name must be mapped to design library [11.2].
    USE DESIGN.BB_PKG.All;
             |
    ncvhdl_p: *E,IDENTU (/projects/MC_E_E1/wrk/ssharma/shi/trunk/src/design/backbone/wb_con/wb_generic.vhd,38|9): identifier (DESIGN) is not declared [10.3].

    This message, which seems to be the cause of most of the following error messages, is saying that the parser doesn't know where to look to find the compiled objects for the BB_PKG package. It doesn't know where the library called "DESIGN" was stored.

    Cadence tools use a file called "cds.lib" to map logical library names to physical disk locations. Search for "cds.lib" in the NCLaunch documentation for help in setting up that mapping file.

    • Post Points: 5
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Started by sonam20 at 18 Jun 2012 02:55 AM. Topic has 7 replies.