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 How to get desired clock skew during CTS? 

Last post Fri, Jun 15 2012 11:20 AM by Tongju. 1 replies.
Started by Tongju 11 Jun 2012 10:27 AM. Topic has 1 replies and 1674 views
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  • Mon, Jun 11 2012 10:27 AM

    • Tongju
    • Top 200 Contributor
    • Joined on Mon, Jul 14 2008
    • San Jose, CA
    • Posts 38
    • Points 505
    How to get desired clock skew during CTS? Reply

    I have a clock that is driving thousands of ffs and the CTS could build a well-balanced tree with about 6ns insertion delay for me. However, to resolve the reg2out timing violations, I like to launch some signals earlear and therefor hope to have shorter clock tree insertion delay (say, 2 ns) for about ten registers (I know their instance names). What is the easiest way to achive this during CTS stage?

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    • Post Points: 5
  • Fri, Jun 15 2012 11:20 AM

    • Tongju
    • Top 200 Contributor
    • Joined on Mon, Jul 14 2008
    • San Jose, CA
    • Posts 38
    • Points 505
    Re: How to get desired clock skew during CTS? Reply

    I figured out the solution: "MacroModel" will do the job!

    • Post Points: 5
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Started by Tongju at 11 Jun 2012 10:27 AM. Topic has 1 replies.