I was designing a LNA which is input matched to 50 Ohm.
It is driving the next stage whose input impedance (MOS input) is very large (it is NOT 50 Ohm matched anyway).
I want to plot this LNA's IIp3/2 using IPN curves. However for that Cadence requires a PORT to be used at the Output of the LNA.
I could NOT understand why it has been done for PORT ? Why it can't take voltage output and calculate/plot the IIP3/2 ?
In chip design the components (inside the chip) need NOT to be matched but Cadence is still using the OLD fashion way of using matched PORT !!
But anyway can anybody please tell how it can be done without using PORT at the output.