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 Simulating verilog using cadence 

Last post Fri, May 11 2012 8:10 PM by MTP3. 1 replies.
Started by MTP3 11 May 2012 11:53 AM. Topic has 1 replies and 3750 views
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  • Fri, May 11 2012 11:53 AM

    • MTP3
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    • Joined on Tue, Jun 7 2011
    • Posts 15
    • Points 195
    Simulating verilog using cadence Reply

    Hi!

     I am new to this forum so please bear with me if my question is basic, anyways here goes. I am trying to simulate a state machine (kind of) in cadence using the ams simulator. NOw I have tested and verified that the design works using model sim. When I try to simulate it using the ams simulator the output appears to x (or connected I assume). Can anyone please guide me what I am doing wrong.

     

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  • Fri, May 11 2012 8:10 PM

    • MTP3
    • Not Ranked
    • Joined on Tue, Jun 7 2011
    • Posts 15
    • Points 195
    Re: Simulating verilog using cadence Reply
    So I figured it out the Dffs had to be reset intially for the circuit to operate I didn't occur to me first as I was treating it as an analog simulation but restting it does the trick.
    • Post Points: 5
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Started by MTP3 at 11 May 2012 11:53 AM. Topic has 1 replies.