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 verilog-a - model ac biasing 

Last post Mon, May 21 2012 2:37 AM by ESTEC. 4 replies.
Started by soathana 10 May 2012 12:52 AM. Topic has 4 replies and 1695 views
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  • Thu, May 10 2012 12:52 AM

    • soathana
    • Top 500 Contributor
    • Joined on Fri, Jan 13 2012
    • Posts 24
    • Points 375
    verilog-a - model ac biasing Reply

    Is there a way to probe simulator as to the biasing conditions of a model implemented in verilog-a ? If not is this possible through verilog-a, via some kind of monitoring scheme or someone must go into spice netlist level? The simulator used is spectre.

     kind regards,

    Sotiris

     

    • Post Points: 20
  • Thu, May 10 2012 5:32 AM

    Re: verilog-a - model ac biasing Reply

    Sotiris,

    It's not that clear to me what you're trying to do. What do you mean by "probe simulator as to the biasing conditions of a model..."? What does that actually mean?

    Maybe you are talking about turning on the saving of internal variables - if so, this can be achieved by turning on saveahdlvars in the Save All form in ADE (or adding "mysaveopts options saveahdlvars=all" or "mysaveops options saveahdlvars=allwithnodes" to your netlist before simulating it).

    Regards,

    Andrew.

    • Post Points: 20
  • Thu, May 10 2012 6:08 AM

    • soathana
    • Top 500 Contributor
    • Joined on Fri, Jan 13 2012
    • Posts 24
    • Points 375
    Re: verilog-a - model ac biasing Reply

    Andrew,

    Sorry for the bad description. What i would like to do is that depending for example on whether a node in my model has an ac source attached to it or a dc source attached to it, affect its behaviour. There are options for example for requesting $time $temperature and analysis("type")  from spectre .Is there a way to probe from the model the spice netlist. i.e. something like if net#=vsin do something if net#=vdc do something else? If not could this be done automatically through SKILL/ other scripted way and redirect information inside verilogA somehow?

    kind regards,

    Sotiris

     

    • Post Points: 20
  • Thu, May 10 2012 6:45 AM

    Re: verilog-a - model ac biasing Reply

    Sotiris,

    That sounds a very odd thing to want to do, and I don't believe it's possible. I can't imagine why you'd ever want to do that...

    Even using $analysis() should be used with caution.

    Regards,

    Andrew.

    • Post Points: 20
  • Mon, May 21 2012 2:37 AM

    • ESTEC
    • Not Ranked
    • Joined on Thu, Apr 19 2012
    • Posts 1
    • Points 5
    Re: verilog-a - model ac biasing Reply

     Andrew,

    Sorry for the late responce. I was on vacations. The thing is that I am impementing some aging effects on BSIM4, and they are partially dependent on past biasing conditions of the circuit. Anyways probably I think I will try with SKILL.

    cheers,

    Sotiris

    • Post Points: 5
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Started by soathana at 10 May 2012 12:52 AM. Topic has 4 replies.