Vpulse and Vsource 

Hi Andrew,

 I was trying to simulate rectifier circuit for which I simulated the circuit to test with different inputs -Sine and Pulse.

Initially, I tried using Vpulse and I observed some result. Then, I replaced Vpulse with Vsine and observed some other result.

 Then I have replaced Vsine with Vsource so that I change the type of input by changing the properties.

I have used the same parameters in Vsource which I have used in Vpulse, but I observed those two results are varying in a huge manner.

Can you please let me know why the difference is happening so? 

In the attached zip file, you can see 5 images. First is the snapshot of the circuit, which I have used for simulation.

Second image is the plot which I have captured, when simulated the circuit using source voltage as Vpulse and third is the plot with Vsource.

Similarly, fourth and fifth plots are captured, when simulated the circuit using source voltage as Vpulse and Vsource respectively.

I have used the same simulation parameters but I do see a change in the plots.

Can you please let me know why it is happening so when I use Vpul and Vsource though I have used zero and one values same in both sources? I have used pulse width as 1.15ns.

Thanks,

Shahnaz. 

Shahnaz,

Given that both a vpulse and a vsource from analogLib will result in an instantiation of spectre's vsource component in the netlist, the best way to figure out why this is happening is to look at the line in the input.scs for the voltage source in both cases and compare the parameters. Fundamentally if the simulator is producing different results, it's rather likely that the input netlist (the input.scs) is different between the two cases.

Let us know what you find!

Regards,

Andrew.

Hi Andrew,

What are the aspects that I should look into input.scs?

Last but not the least, Where should I find input.scs file?

Thanks in advance.

Shahnaz 

Shahnaz,

Well, you can simply use Simulation->Netlist->Display in ADE and it will show it to you. Look in the file for a line containing "vsource" - it will probably be near the end, since it's presumably in your top level testbench - and the line will start with (say) V1 if the instance name on the schematic of the source was V1...

Andrew.

Andrew,

Thanks for your support. I am now clear, that the variations whatever I had observed, is not due to the Vpulse or Vsource from the analoglib.

I have checked the input.scs file and found all the simulation parameters to be same.

When debugged further, I came to a conclusion, that swapping the voltages given to zero and one values has lead to the variation in the results.

Till now, I felt that whether I swap voltages given to zero and one value, it should not matter. Result should be same.

In order to continue this experiment, I have varied the values given to zero and one in Vpul.

Initially, I had given zero as 0V and one as 100mV. Later I swapped zero and one values and so now, zero is 150mV and one is 0V.

Later, I put zero as 50mV and one as -50mV.

Ideally speaking, the circuit should not work for that voltage. When the input voltage is greater than Vth of the MOS (400mV), circuit will start giving output else output is zero.

I have attached the waveforms associated with it.

Now my question, why is it showing output as ramp down from 95.6mV when zero is 100mV. and one is 0V. Output is ramp up from zero to 350uV, when zero is 0V and one is 100mV. when zero is -50mV and one i s50mV,  output is again ramp down from 39mV. I am confused with this behaviour.

I,somehow, feel that output is generated by taking the zero value of the input as an reference value.

Can you please let me know why the behaviour is so?

Awaiting for your reply.

PS: first image in the zip file is when zero value is 50mV and one value is -50mV.

Second image in zip file is when zero is 100mV and one is 0V.

Last is when zero is 0V and one is 100mV 

Thanks,

Shahnaz 

I can't really debug your circuit for you from a picture of the schematic in your first attachment and the waveforms in the new one. It does look a slight strange configuration - not quite sure what you're testing here. The bulk of the PMOS transistors is connected to the output - and there's no DC level for the gates - so there's quite a lot that's actually floating here - the behaviour of the PMOS transistors will be dependent upon what the gate and source voltages are relative to the bulk. The DC solution at the beginning of the simulation will be based on the time-zero values of the sources, and that will probably affect the initial voltage on the output capacitor - and you'll also get coupling through the junction capacitances on the transistor, as well as  the behaviour when (or if) the transistors switch.

Remember that the DC solution (e.g. the initial transient solution) is based on setting all the capacitances (both explicit capacitors and the capacitances inside the transistor models) to 0, and solving the equations. With no DC path to ground, you'll get gmin resistors inserted at various places to try to come up with a DC solution - but that's going to be influenced by whatever the time zero value of the source is. You didn't say how the source is varying (what timescale), and whether these small variations are important (in none of the cases are the signal levels varying that much - it's just the starting point which is different).

So I think it's possibly something to do with the DC starting point, but other than that, you'll need to figure it out yourself.

Regards,

Andrew.