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 How to debug VerilogA compilation when code seems to check clean but simulation aborts when compiling ? 

Last post Wed, May 9 2012 8:31 AM by Herge. 3 replies.
Started by Herge 09 May 2012 07:44 AM. Topic has 3 replies and 1656 views
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  • Wed, May 9 2012 7:44 AM

    • Herge
    • Top 500 Contributor
    • Joined on Fri, May 8 2009
    • Oudenaarde, Belgium
    • Posts 17
    • Points 235
    How to debug VerilogA compilation when code seems to check clean but simulation aborts when compiling ? Reply

    Hello I have a verilogA module using multi-terminal ports and where I want to use for loops to assign all currents. I took care to use genvars, and I don't get any syntax error during the check after saving the verilogA view. However during simulation, spectre is aborting (very laconically, even if I use option +debug).

    ** Below the header of my module :

      module qnrmesh2d(majport,minport);
       
       // Majority carriers terminals  
       inout [1:`QNRMESH2D_NPORTS] majport;
       electrical [1:`QNRMESH2D_NPORTS] majport;

       // Minority carriers terminals  
       inout [1:`QNRMESH2D_NPORTS] minport;
       electrical [1:`QNRMESH2D_NPORTS] minport;

     ...

    **  Below the declarations of my genvars :

        genvar    thisPort, otherPort, refPort; 

    **  Below a typical set of loops

         // Trick to define the reference port
          for (refPort = `QNRMESH2D_NPORTS; refPort == `QNRMESH2D_NPORTS; refPort = refPort + 1) begin

              // Generate the charge balance equations at all ports
              for (thisPort = 1; thisPort < `QNRMESH2D_NPORTS; thisPort = thisPort + 1) begin

                  // Extract the quasi-Fermi potential and evaluate its exponential
                  Imref_min[thisPort] = sq_min*V(minport[thisPort],majport[thisPort]);
                  LimExpImref = limexp(Imref_min[thisPort]/$vt);
                 ...

                  // Loop over all ports to compute the current in the selected port (thisPort)
                 for (otherPort = 1; otherPort < `QNRMESH2D_NPORTS; otherPort = otherPort + 1) begin

                      // Assign the drift majority current
                     I(majport[thisPort],majport[refPort]) <+ Gdrift_maj[`index2D(`QNRMESH2D_NPORTS,thisPort,otherPort)]
                                                                               *V(majport[otherPort],majport[refPort]);
                 ...
                 end
           end
    end

    ** ICFB message when saving :

              veriloga Diagnostics: Warnings exist in veriloga text of cell qnrmesh2d.
              Abort

     ** Spectre.out contains nothing beyond the lines "Loading ..lib...so"

    • Post Points: 20
  • Wed, May 9 2012 7:55 AM

    Re: How to debug VerilogA compilation when code seems to check clean but simulation aborts when compiling ? Reply

    It sounds as if spectre is aborting both during the check (hence the Abort message) and also during simulation. In order to check this, we'd need to know which spectre version you're using (the subversion should show in the spectre output log file), and also the full Verilog-A model.

    If you can't post that here, please contact Customer Support.

    Regards,

    Andrew.

    • Post Points: 5
  • Wed, May 9 2012 8:04 AM

    • Herge
    • Top 500 Contributor
    • Joined on Fri, May 8 2009
    • Oudenaarde, Belgium
    • Posts 17
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    Re: How to debug VerilogA compilation when code seems to check clean but simulation aborts when compiling ? Reply

     Andrew,

     The spectre version is : 10.1.1.092.isr7 32bit -- 22 Apr 2011.

     For the complete code I'll go via the support line. 

    • Post Points: 5
  • Wed, May 9 2012 8:31 AM

    • Herge
    • Top 500 Contributor
    • Joined on Fri, May 8 2009
    • Oudenaarde, Belgium
    • Posts 17
    • Points 235
    Re: How to debug VerilogA compilation when code seems to check clean but simulation aborts when compiling ? Reply
    See support request nbr : 42907042 (it has the complete files attached).
    • Post Points: 5
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Started by Herge at 09 May 2012 07:44 AM. Topic has 3 replies.