The thing is the design contain some memory, but memory complier is not available for hardening the memory. While optimising the rest of the logic, the memory which is realised as flops are also optimised. Reason is SoC encounter see these flops as just instances/standard cell.
As a result, timing cant be closed at desired frequency & is also leading to very high setup & hold violations.
So how to optimise the rest of the design without touching the memory part.