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 Simulating CMOS D type FF as divide by two but using Vss = -6 and Vdd = 0 

Last post Thu, May 3 2012 10:38 AM by OldJohnnyBoy. 0 replies.
Started by OldJohnnyBoy 03 May 2012 10:38 AM. Topic has 0 replies and 447 views
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  • Thu, May 3 2012 10:38 AM

    Simulating CMOS D type FF as divide by two but using Vss = -6 and Vdd = 0 Reply

    I have a CMOS digital circuit with normal supply of +5V.  I need to include a D type divide by 2 circuit that has a separate supply of Vss = -6 and Vdd = 0 v. The clock input is derived from the normal logic by a resistive potential divider. How do I achieve this dual power supply?  I cannot decide if I have a power supply problem or a digital divider problem since the clock signal is exactly as predicted but no divider digital output, or perhaps, both power supply and digital divider problems.

    I am using Pspice A/D, transient analysis

    Kind regards

    OldJohnnyBoy

    • Post Points: 5
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Started by OldJohnnyBoy at 03 May 2012 10:38 AM. Topic has 0 replies.