When there is clock gating logic, do I have to define the gated clock as a generated clock in my constraint file for a proper STA?
I don't know if anybody is familiar with this great book, but my question came up because I saw an example in the book "Static Timing Analysis for Nanometer Design: A practical Approach". Figure 7-12 shows an example where a clock is gated by the output of a flip-flop and then they wrote a SDC constraint to define the gated clock. See below:create_clock 0.1 [get_ports SYS_CLK]
# Create a master clock of period 100ps with 50% duty cycle.
create_generated_clock -name CORE_CLK -divide_by 1 -source SYS_CLK [get_pins UAND1/Z]
# Create a generated clock called CORE_CLK at the output of the and cell and the clock
The book says: "Figure 7-12 shows an example where the clock SYS_CLK is gated by the output of a flip-flop. Since the output of the flip-flop may not be a constant, one way to handle this situation is to define a generated clock at the output of the and cell which is identical to the input clock."
Must I define all gated clocks as new generated clocks in my SDC file?
The book mentiones that is one way to handle the situation, what are other ways to handle this situation?
Your input is much appreciated.